Intel® MAX® 10 High-Speed LVDS I/O User Guide

ID 683760
Date 10/02/2023
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3.4.1.2.24.3.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Receiver3.4.1.2.24.3.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Receiver

To determine the ALTPLL IP core clock parameter for the Soft LVDS IP core receiver, follow these steps in your design:
  1. Instantiate the Soft LVDS IP core receiver using internal PLL.
  2. Compile the design up to Timing Analyzer timing analysis.
  3. In the Table of Contents section of the Compilation Report window, navigate to Timing Analyzer > Clocks.
  4. Note the clock parameters used by the internal PLL for the Soft LVDS IP core receiver.
    In the list of clocks, clk[0] is the fast clock, clk[1] is the slow clock, and clk[2] is the read clock.
Figure 14. Figure 24. Clock Parameters Example for Soft LVDS Receiver


Configure the ALTPLL output clocks with the parameters you noted in this procedure and connect the clock outputs to the correct Soft LVDS clock input ports.