3.4.3. Guidelines: LVDS Transmitter Channels Placement
Intel recommends that you create an Intel® Quartus® Prime design, specify your device I/O assignments, and compile your design to validate your pin placement. The Intel® Quartus® Prime software verifies your pin connections against the I/O assignment and placement rules to ensure that the device operates properly.
You can use the Intel® Quartus® Prime Pin Planner Package view to ease differential I/O assignment planning:
- On the View menu, click Show Differential Pin Pair Connections to highlight the differential pin pairing. The differential pin pairs are connected with red lines.
- For differential pins, you only need to assign the signal to a positive pin. The Intel® Quartus® Prime software automatically assigns the negative pin if the positive pin is assigned with a differential I/O standard.
In Intel® MAX® 10 devices, the routing of each differential pin pair is matched. Consequently, the skew between the positive and the negative pins is minimal. The internal routes of both pins in a differential pair are matched even if the pins are non-adjacent.
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