Intel® MAX® 10 High-Speed LVDS I/O User Guide

ID 683760
Date 10/02/2023
Public
Document Table of Contents
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4.3.1.4. Guidelines: Applying Input Delay Constraint for LVDS SERDES Receiver

You can use the additional set_input_delay to constraint the external input delay requirements. Specify the clock (-clock) to reference the virtual clock to allow the Timing Analyzer to correctly derive clock uncertainties for interclock and intraclock transfers.
#create the virtual clock for external input

create_clock -name virtual_clock -period "100 MHz"

#define max lvds_input_delay

set lvds_input_delay_max [expr 0.3]

#define min lvds_input_delay

set lvds_input_delay_min [expr 0.1]

#constraint external input min/max delay

set_input_delay -clock { virtual_clock } -min $lvds_input_delay_min [get_ports {rx_in*}]

set_input_delay -clock { virtual_clock } -max $lvds_input_delay_max [get_ports {rx_in*}]

set_input_delay -clock { virtual_clock } -clock_fall -min $lvds_input_delay_min [get_ports {rx_in*}] -add_delay

set_input_delay -clock { virtual_clock } -clock_fall -max $lvds_input_delay_max [get_ports {rx_in*}] -add_delay

The virtual clock frequency must be the same as the LVDS SERDES IP inclock. The minimum or maximum of the lvds_input_delay value depends on the channel-to-channel skew from the driver source. For example, the skew can be contributed by the TCCS of the source and board skew.