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1. Intel® MAX® 10 High-Speed LVDS I/O Overview
2. Intel® MAX® 10 High-Speed LVDS Architecture and Features
3. Intel® MAX® 10 LVDS Transmitter Design
4. Intel® MAX® 10 LVDS Receiver Design
5. Intel® MAX® 10 LVDS Transmitter and Receiver Design
6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations
7. Soft LVDS IP Core References
8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives
9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
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3.4.1.1.1. Instantiate Soft LVDS IP Core with Internal PLL
You can set the Soft LVDS IP core to build the SERDES components and instantiate the PLL internally.
- To use this method, turn off the Use external PLL option in the PLL Settings tab and set the necessary settings in the PLL Settings and Transmitter Settings tab.
- The Soft LVDS IP core integrates the PLL into the LVDS block.
- The drawback of this method is that you can use the PLL only for the particular LVDS instance.
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