1. Intel® MAX® 10 High-Speed LVDS I/O Overview 2. Intel® MAX® 10 High-Speed LVDS Architecture and Features 3. Intel® MAX® 10 LVDS Transmitter Design 4. Intel® MAX® 10 LVDS Receiver Design 5. Intel® MAX® 10 LVDS Transmitter and Receiver Design 6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations 7. Soft LVDS IP Core References 8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives 9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
5.2.2. Initializing the Soft LVDS IP Core
The PLL locks to the reference clock before the Soft LVDS IP core implements the SERDES blocks for data transfer.
During device initialization the PLL starts to lock to the reference clock and becomes operational when it achieves lock during user mode. If the clock reference is not stable, it corrupts the phase shifts of the PLL output clock. This phase shifts corruption can cause failure and corrupt data transfer between the high-speed LVDS domain and the low-speed parallel domain.
To avoid data corruption, follow these steps when initializing the Soft LVDS IP core:
- Assert the pll_areset signal for at least 10 ns.
- After at least 10 ns, deassert the pll_areset signal.
- Wait until the PLL lock becomes stable.
After the PLL lock port asserts and is stable, the SERDES blocks are ready for operation.
Did you find the information on this page useful?