Intel® MAX® 10 High-Speed LVDS I/O User Guide

ID 683760
Date 10/02/2023
Public
Document Table of Contents
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4.3. LVDS Receiver FPGA Design Implementation

Intel® MAX® 10 devices use a soft SERDES architecture to support high-speed I/O interfaces. The Intel® Quartus® Prime software creates the SERDES circuits in the core fabric by using the Soft LVDS IP core. To improve the timing performance and support the SERDES, Intel® MAX® 10 devices use the I/O registers and LE registers in the core fabric.