1. MAX® 10 High-Speed LVDS I/O Overview
2. MAX® 10 High-Speed LVDS Architecture and Features
3. MAX® 10 LVDS Transmitter Design
4. MAX® 10 LVDS Receiver Design
5. MAX® 10 LVDS Transmitter and Receiver Design
6. MAX® 10 High-Speed LVDS Board Design Considerations
7. Soft LVDS Intel® FPGA IP Core References
8. MAX® 10 High-Speed LVDS I/O User Guide Archives
9. Document Revision History for the MAX® 10 High-Speed LVDS I/O User Guide
4.3.3. Guidelines: Floating LVDS Input Pins
You can implement floating LVDS input pins in MAX® 10 devices.
For floating LVDS input pins, apply a 100 Ω differential resistance across the P and N legs of the LVDS receiver. You can use external termination.
If you use floating LVDS input pins, Altera recommends that you use external biasing schemes to reduce noise injection and current consumption.