1. MAX® 10 High-Speed LVDS I/O Overview
2. MAX® 10 High-Speed LVDS Architecture and Features
3. MAX® 10 LVDS Transmitter Design
4. MAX® 10 LVDS Receiver Design
5. MAX® 10 LVDS Transmitter and Receiver Design
6. MAX® 10 High-Speed LVDS Board Design Considerations
7. Soft LVDS Intel® FPGA IP Core References
8. MAX® 10 High-Speed LVDS I/O User Guide Archives
9. Document Revision History for the MAX® 10 High-Speed LVDS I/O User Guide
6.2. Guidelines: Control Channel-to-Channel Skew
For the MAX® 10 devices, perform PCB trace compensation to adjust the trace length of each LVDS SERDES channel. Adjusting the trace length improves the channel-to-channel skew when interfacing with receivers.
At the package level, you must control the LVDS SERDES channel skew for each I/O bank and each side of the device. If you plan to vertically migrate from one device to another using the same board design, you must control the package migration skew for each migratable LVDS I/O pin.
For information about controlling the LVDS I/O and package skew, refer to the related information.