Intel® MAX® 10 High-Speed LVDS I/O User Guide

ID 683760
Date 10/02/2023
Document Table of Contents
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6.3. Guidelines: Determine Board Design Constraints

After you have closed timing for your FPGA design, examine your board design to determine the different factors that can impact signal integrity. These factors affect overall timing at the receiving device in the LVDS interface.

The time margin for the LVDS receiver (indicated by the RSKM value) is the timing budget allocation for board level effects such as:

  • Skew—these factors cause board-level skew:
    • Board trace lengths
    • Connectors usage
    • Parasitic circuits variations
  • Jitter—jitter effects are derived from factors such as crosstalk.
  • Noise—on board resources with imperfect power supplies and reference planes may also cause noise.

To ensure successful operation of the Soft LVDS IP core receiver, do not exceed the timing budget.