- Added short descriptions about the true and emulated LVDS buffers.
- Added single power supply U324 package.
- Updated the topic about using the Soft LVDS IP core (receiver) in external PLL mode to remove the ALTPLL IP core slow clock output (c1) connection to the Soft LVDS rx_synclock input for even deserialization factor. The rx_synclock is not used by the Soft LVDS IP core when the deserialization factor is even.
- Updated the section about high-speed I/O timing budget:
- Updated the high-speed I/O timing budget topic to clarify that Intel® MAX® 10 devices implements SERDES in LEs.
- Removed information about obtaining RSKM report in the Intel® Quartus® Prime software. The software does not support generating RSKM report for Intel® MAX® 10 devices.
- Removed the topic about assigning input delay to the LVDS receiver.
- Added link to timing constraints section of the Intel Quartus Prime Standard Edition Handbook Volume 3: Verification.
- Updated the condition and description for the Enable pll_areset port parameter to specify that it is not available in external PLL mode.
- Throughout the document, added links to related information to improve usability.
- Further edits for Intel rebranding.
||Rebranded as Intel.
- Added related information links in the topic about LVDS channels support.
- Restructured and updated the topic about the RSKM.
- Added a topic that describes how to assign input delay to the LVDS receiver using the Timing Analyzer.
- Added true RSDS and emulated RSDS (three resistors) transmitter support for single supply Intel® MAX® 10 devices.
- Updated the transmitter and receiver channels placement topics to describe about minimizing skew when you group LVDS channels for an application.
- Updated the description of the rx_data_reset interface signal to specify that you must externally synchronize it with the fast clock.
- Updated the General tab of the Soft LVDS parameter settings:
- Added the Power Supply Mode option.
- Updated the allowed values of the SERDES factor parameter.
- Updated the high-speed LVDS circuitry figure to correct the flow from C1 in ALTPLL to inclock of ALTERA_SOFT_LVDS. Previously, the figure shows a bidirectional flow.
- Updated the steps for determining the external PLL clock parameters for the receiver to clarify the clock names listed by the Intel® Quartus® Prime compilation report.
- Updated the topic about Soft LVDS parameter settings:
- Added links to topics about PLL and high-speed I/O performance in the device datasheet.
- Corrected the conditions required to use the Enable tx_data_reset port and Enable rx_data_reset port parameters. You must turn on the Use external PLL option first.
- Updated the allowed values for the Tx_outclock division factor and Outclock duty cycle parameters.
- Updated the condition for the Desired transmitter outclock phase shift parameter.
- Removed the topics about generating IP cores and the files generated by the IP core, and added a link to Introduction to Altera IP Cores.
- Removed the statement about getting TCCS value from the Intel® Quartus® Prime compilation report. You can get TCCS value from the device datasheet.
- Added guidelines topic about enabling LVDS pre-emphasis for Intel® MAX® 10 devices in the E144 package.
- Updated the guidelines to control channel-to-channel skew to remove statements about getting the trace delay amount from the Fitter Report panel.
- Added link to video that demonstrates how to generate IBIS file using the Intel® Quartus® Prime software.
- Changed instances of Quartus II to Quartus Prime.
- Removed the F672 package from the 10M25 device.
- Updated the number of bottom true receiver channels for package M153 of the 10M02 device from 49 to 13.
- Added BLVDS output support in single-supply Intel® MAX® 10 devices. Previously, BLVDS support for single-supply devices was input only.
- Updated the RSKM definition in the topic about receiver input skew margin to include jitter induced from core noise and I/O switching noise.
- Updated topics related to using the Soft LVDS IP core (transmitter or receiver) in external PLL mode:
- Added rx_readclock, rx_syncclock, and tx_synclock ports.
- Removed pll_areset port.
- Added examples for odd and even serialization factors.
- Added procedures to obtain the external PLL clock parameters.
- Removed similar guidelines in the chapter for the transmitter and receiver design. The updated guidelines for the receiver only and transmitter only designs can apply for designs that use both transmitters and receivers.
- Updated parameter settings of the Soft LVDS IP core:
- Removed allowed values "6" and "9" from the SERDES factor parameter.
- Added allowed value "Off" to the Enable pll_areset port parameter.
- Updated the parameter label Register_rx_bitslip_ctrl port to Add extra register for rx_data_align port and specified that you must pre-register the port if you turn it on.
- Updated table listing LVDS channels to include LVDS channel counts for each device package.
- Added information in the topics about channels placement that Intel® MAX® 10 devices support x18 bundling mode.
- Updated the examples in topics about channels PLL placement to provide more details.
- Added link to the MAX 10 Clocking and PLL User Guide that provides more information about the PLL and the PLL output counters used to clock the soft SERDES.
| September 2014
|| Initial release.