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1. Intel® MAX® 10 High-Speed LVDS I/O Overview
2. Intel® MAX® 10 High-Speed LVDS Architecture and Features
3. Intel® MAX® 10 LVDS Transmitter Design
4. Intel® MAX® 10 LVDS Receiver Design
5. Intel® MAX® 10 LVDS Transmitter and Receiver Design
6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations
7. Soft LVDS Intel® FPGA IP Core References
8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives
9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
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9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
Document Version | Intel® Quartus® Prime Version | Changes |
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2023.10.02 | 22.1 | Added the Guidelines: Applying Input Delay Constraint for LVDS SERDES Receiver section. |
2022.10.31 | 22.1 |
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2021.11.01 | 21.1 |
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Date | Version | Changes |
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December 2017 | 2017.12.15 |
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February 2017 | 2017.02.21 | Rebranded as Intel. |
October 2016 | 2016.10.31 |
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May 2016 | 2016.05.02 |
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November 2015 | 2015.11.02 |
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May 2015 | 2015.05.04 |
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December 2014 | 2014.12.15 |
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September 2014 | 2014.09.22 | Initial release. |