1. Intel® MAX® 10 High-Speed LVDS I/O Overview 2. Intel® MAX® 10 High-Speed LVDS Architecture and Features 3. Intel® MAX® 10 LVDS Transmitter Design 4. Intel® MAX® 10 LVDS Receiver Design 5. Intel® MAX® 10 LVDS Transmitter and Receiver Design 6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations 7. Soft LVDS IP Core References 8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives 9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
184.108.40.206. Guidelines: LVDS Receiver Timing Constraints
For receiver designs that uses the core logic to implement the SERDES circuits, you must set proper timing constraints.
For LVDS receiver data paths where the PLL operation is in source-synchronous compensation mode, the Intel® Quartus® Prime compiler automatically ensures that the associated delay chain settings are set correctly.
However, if the input clock and data at the receiver are not edge- or center-aligned, it may be necessary for you to set the timing constraints in the Intel® Quartus® Prime Timing Analyzer. The timing constraints specify the timing requirements necessary to ensure reliable data capture.
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