188.8.131.52. Guidelines: LVDS Receiver Timing Constraints
For LVDS receiver data paths where the PLL operation is in source-synchronous compensation mode, the Intel® Quartus® Prime compiler automatically ensures that the associated delay chain settings are set correctly.
However, if the input clock and data at the receiver are not edge- or center-aligned, it may be necessary for you to set the timing constraints in the Intel® Quartus® Prime Timing Analyzer. The timing constraints specify the timing requirements necessary to ensure reliable data capture.