1. Intel® MAX® 10 High-Speed LVDS I/O Overview 2. Intel® MAX® 10 High-Speed LVDS Architecture and Features 3. Intel® MAX® 10 LVDS Transmitter Design 4. Intel® MAX® 10 LVDS Receiver Design 5. Intel® MAX® 10 LVDS Transmitter and Receiver Design 6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations 7. Soft LVDS IP Core References 8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives 9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
184.108.40.206. Guidelines: LVDS RX Interface Using External PLL
You can instantiate the Soft LVDS IP core with the Use External PLL option. Using external PLL, you can control the PLL settings. For example, you can dynamically reconfigure the PLL to support different data rates and dynamic phase shifts. To use this option, you must instantiate the ALTPLL IP core to generate the various clock signals.
If you turn on the Use External PLL option for the Soft LVDS receiver, you require the following signals from the ALTPLL IP core:
- Serial clock input to the rx_inclock port of the Soft LVDS receiver.
- Parallel clock used to clock the receiver FPGA fabric logic.
- The locked signal for Soft LVDS PLL reset port.
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