Low Latency 40-Gbps Ethernet IP Core User Guide

ID 683745
Date 3/08/2021
Document Table of Contents
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1. About the LL 40GbE IP Core

Updated for:
Intel® Quartus® Prime Design Suite 16.1

The Intel®  Low Latency 40 -Gbps Ethernet (LL 40GbE) media access controller (MAC) and PHY Intel® FPGA IP functions offer the lowest round-trip latency and smallest size to implement the IEEE 802.3ba High Speed Ethernet Standard with an option to support the IEEE 802.3ap-2007 Backplane Ethernet Standard.

The version of this product that supports Intel® Arria® 10 devices is included in the Intel FPGA IP Library and is available from the Intel® Quartus® Prime IP Catalog.

Note: The full product name, Low Latency 40 -Gbps Ethernet MAC and PHY Intel® FPGA IP Function, is shortened to Low Latency (LL) 40 GbE (LL 40GbE) IP core in this document. In addition, although multiple variations are available from the parameter editor, this document refers to this product as a single IP core, because all variations are configurable from the same parameter editor.
Figure 1.  LL 40GbE IP CoreMain blocks, internal connections, and external block requirements.

As illustrated, on the MAC client side you can choose a wide, standard Avalon® streaming interface (Avalon-ST), or a narrower, custom streaming interface. The MAC client side Avalon® streaming interface data bus is 256 bits wide. The MAC client side custom streaming interface data bus is 127 bits wide. The client-side data maps to four 10.3125 Gbps transceiver PHY links.

The 40GbE (XLAUI) interface has 4x10.3125 Gbps links. For Intel® Arria® 10 devices only, you can configure a 40GbE 40GBASE-KR4 variation to support Backplane Ethernet.

The FPGA serial transceivers are compliant with the IEEE 802.3ba standard XLAUI specification . You can connect the transceiver interfaces directly to an external physical medium dependent (PMD) optical module or to another device.

The IP core provides standard MAC and physical coding sublayer (PCS) functions with a variety of configuration and status registers. You can exclude the statistics registers. If you exclude these registers, you can monitor the statistics counter increment vectors that the IP core provides at the client side interface and maintain your own counters.