Low Latency 40-Gbps Ethernet IP Core User Guide

ID 683745
Date 3/08/2021
Document Table of Contents

2.7.3. Transceiver PLL Required in Arria 10 Designs

LL 40GbE IP cores that target an Arria 10 device require an external TX transceiver PLL to compile and to function correctly in hardware.

Figure 7. PLL Configuration ExampleIn this example, the TX transceiver PLL is instantiated with an Arria 10 ATX PLL IP core. The TX transceiver PLL must always be instantiated outside the LL 40GbE IP core.

In this example, Use external TX MAC PLL is turned off. Therefore, the TX MAC PLL is in the IP core. If you turn on the Use external TX MAC PLL parameter you must also instantiate and connect a TX MAC PLL outside the LL 40GbE IP core.

You can use the IP Catalog to create a transceiver PLL.

  • Select Arria 10 Transceiver ATX PLL or Arria 10 Transceiver CMU PLL.
  • In the parameter editor, set the following parameter values:
    • PLL output frequency to 5156.25 MHz . The transceiver performs dual edge clocking, using both the rising and falling edges of the input clock from the PLL. Therefore, this PLL output frequency setting supports a 10.3125 data rate through the transceiver.
    • PLL reference clock frequency to the value you specified for the PHY reference frequency parameter.

When you generate a LL 40GbE IP core, the software also generates the HDL code for an ATX PLL, in the file <variation_name> /arria10_atx_pll.v. However, the HDL code for the LL 40GbE IP core does not instantiate the ATX PLL. If you choose to use the ATX PLL provided with the LL 40GbE IP core, you must instantiate and connect the instances of the ATX PLL with the LL 40GbE IP core in user logic.

Note: If your Arria 10 design includes multiple instances of the LL 40GbE IP core, do not use the ATX PLL HDL code provided with the IP core. Instead, generate new TX PLL IP cores to connect in your design.

The number of external PLLs you must generate or instantiate depends on the distribution of your Ethernet TX serial lines across physical transceiver channels and banks. You specify the clock network to which each PLL output connects by setting the clock network in the PLL parameter editor. The example project demonstrates one possible choice, which is compatible with the ATX PLL provided with the LL 40GbE IP core.

You must connect the tx_serial_clk input pin for each LL 40GbE IP core PHY link to the output port of the same name in the corresponding external PLL. You must connect the pll_locked input pin of the LL 40GbE IP core to the logical AND of the pll_locked output signals of the external PLLs for all of the PHY links.

User logic must provide the AND function and connections. Refer to the example compilation project or design example for working user logic that demonstrates one correct method to instantiate and connect an external PLL.