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2.1. Installation and Licensing for LL 40GbE IP Core for Stratix® V Devices
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Core Parameters and Options
2.4. IP Core Parameters
2.5. Files Generated for Stratix V Variations
2.6. Files Generated for Arria 10 Variations
2.7. Integrating Your IP Core in Your Design
2.8. IP Core Testbenches
2.9. Compiling the Full Design and Programming the FPGA
2.10. Initializing the IP Core
2.7.1. Pin Assignments
2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs
2.7.3. Transceiver PLL Required in Arria 10 Designs
2.7.4. Handling Potential Jitter in Intel® Arria® 10 Devices
2.7.5. External Time-of-Day Module for Variations with 1588 PTP Feature
2.7.6. Clock Requirements for 40GBASE-KR4 Variations
2.7.7. External TX MAC PLL
2.7.8. Placement Settings for the LL 40GbE Core
2.8.2.1. Generating the LL 40GbE Testbench
2.8.2.2. Optimizing the IP Core Simulation With the Testbenches
2.8.2.3. Optimization in the 40GBASE-KR4 Testbench
2.8.2.4. Simulating with the Modelsim Simulator
2.8.2.5. Simulating with the NCSim Simulator
2.8.2.6. Simulating with the VCS Simulator
2.8.2.7. Testbench Output Example
3.2.1. LL 40GbE IP Core TX Datapath
3.2.2. LL 40GbE IP Core TX Data Bus Interfaces
3.2.3. LL 40GbE IP Core RX Datapath
3.2.4. LL 40GbE IP Core RX Data Bus Interfaces
3.2.5. External Reconfiguration Controller
3.2.6. External Transceiver PLL
3.2.7. External TX MAC PLL
3.2.8. Congestion and Flow Control Using Pause Frames
3.2.9. Pause Control and Generation Interface
3.2.10. Pause Control Frame Filtering
3.2.11. Link Fault Signaling Interface
3.2.12. Statistics Counters Interface
3.2.13. 1588 Precision Time Protocol Interfaces
3.2.14. PHY Status Interface
3.2.15. Transceiver PHY Serial Data Interface
3.2.16. Low Latency 40GBASE-KR4 IP Core Variations
3.2.17. Control and Status Interface
3.2.18. Arria 10 Transceiver Reconfiguration Interface
3.2.19. Clocks
3.2.20. Resets
3.2.2.1. LL 40GbE IP Core User Interface Data Bus
3.2.2.2. LL 40GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)
3.2.2.3. LL 40GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface)
3.2.2.4. Bus Quantization Effects With Adapters
3.2.2.5. User Interface to Ethernet Transmission
3.2.3.1. LL 40GbE IP Core RX Filtering
3.2.3.2. LL 40GbE IP Core Preamble Processing
3.2.3.3. IP Core Strict SFD Checking
3.2.3.4. LL 40GbE IP Core FCS (CRC-32) Removal
3.2.3.5. LL 40GbE IP Core CRC Checking
3.2.3.6. LL 40GbE IP Core Malformed Packet Handling
3.2.3.7. RX CRC Forwarding
3.2.3.8. Inter-Packet Gap
3.2.3.9. Pause Ignore
3.2.3.10. Control Frame Identification
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A. Arria 10 10GBASE-KR Registers
This appendix duplicates the 10GBASE-KR PHY register listings from the Arria 10 Transceiver PHY User Guide. Intel provides this appendix as a convenience to make the full LL 40GBASE-KR4 register information available in the LL 40GbE IP core user guide. While Intel makes every attempt to keep the information in the appendix up-to-date, the most up-to-date information is always found in the Arria 10 Transceiver PHY User Guide, and the appendix is not guaranteed to be up-to-date at any particular time.
Most LL 40GBASE-KR4 registers are 10GBASE-KR PHY registers of the Arria 10 10GBASE-KR PHY IP core, documented in the Arria 10 Transceiver PHY User Guide and duplicated, with a potential time lag for updates, in this appendix. The register offsets differ by 0x400 in the 40GBASE-KR4 variations of the LL 40GbE IP core. The LL 40GBASE-KR4 variations of the LL 40GbE IP core have additional LL 40GBASE-KR4 related registers and register fields.
LL 40GBASE-KR4 Registers documents the differences between the 10GBASE-KR PHY register definitions in the 10GBASE-KR PHY Register Defintions section of the 10GBASE-KR PHY IP Core section in the Arria 10 Transceiver PHY User Guide and the 40GBASE-KR4 registers of the LL 40GbE IP core. All Arria 10 10GBASE-KR PHY registers and register fields not listed in LL 40GBASE-KR4 Registers are available in the 40GBASE-KR4 variations of the LL 40GbE IP core.
Where the Arria 10 Transceiver PHY User Guide and this appendix list 10GBASE-R, substitute 40GBASE-KR4 with auto-negotiation and link training both turned off, and where they list 10GBASE-KR (except in the description of 0x4CB[24:0]), substitute 40GBASE-KR4. Where a register field description in the Arria 10 Transceiver PHY User Guide and this appendix refers to link training or FEC in the single-lane 10GBASE-KR PHY IP core, substitute link training or FEC on Lane 0 of the LL 40GBASE-KR4 IP core variation.
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