2.8.2. Simulating the LL 40GbE IP Core With the Testbenches
You can simulate the LL 40GbE IP core using the Intel-supported versions of the Mentor Graphics ModelSim® SE, Cadence NCSim, and Synopsys VCS simulators for the current version of the Quartus Prime software. The ModelSim® - Intel FPGA Edition simulator does not have the capacity to simulate this IP core.
The example testbenches simulate packet traffic at the digital level. The testbenches do not require special SystemVerilog class libraries.
The example testbenches contain the test files and run scripts for the ModelSim, Cadence, and Synopsys simulators. The run scripts use the file lists in the wrapper files. When you launch a simulation from the original directory, the relative filenames in the wrapper files allow the run script to locate the files correctly. When you generate the testbench for a LL 40GbE IP core that targets an Arria 10 device, the software generates a copy of the IP core variation with a specific relative path from the testbench scripts.
Testbench and Simulation Files
|Top-level testbench file for non-40GBASE-KR4 variations. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.
|Top-level testbench file for 40GBASE-KR4 variations.
|alt_e40_avalon_tb_packet_gen.v, alt_e40_avalon_tb_packet_gen_sanity_check.v, alt_e40_stat_cntr_1port.v
|Packet generator and checkers for 40GBASE-KR4 variations.
The ModelSim script to run the testbench.
Note: The ModelSim® - Intel FPGA Edition simulator does not have the capacity to simulate this IP core. You must use another supported ModelSim simulator.
The Synopsys VCS script to run the testbench.
The Cadence NCSim script to run the testbench.