Low Latency 40-Gbps Ethernet IP Core User Guide

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ID 683745
Date 3/08/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the LL 40GbE IP Core 2. Getting Started 3. Functional Description 4. Debugging the Link A. Arria 10 10GBASE-KR Registers B. Additional Information
1. About the LL 40GbE IP Core x
1.1. LL 40GbE IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. LL 40GbE IP Core Device Family Support 1.2.2. LL 40GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Arria 10 Resource Utilization 1.4.2. Stratix V Resource Utilization
2. Getting Started x
2.1. Installation and Licensing for LL 40GbE IP Core for Stratix® V Devices 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options 2.4. IP Core Parameters 2.5. Files Generated for Stratix V Variations 2.6. Files Generated for Arria 10 Variations 2.7. Integrating Your IP Core in Your Design 2.8. IP Core Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.2. Installing and Licensing Intel® FPGA IP Cores x
2.2.1. Intel® FPGA IP Evaluation Mode
2.7. Integrating Your IP Core in Your Design x
2.7.1. Pin Assignments 2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.7.3. Transceiver PLL Required in Arria 10 Designs 2.7.4. Handling Potential Jitter in Intel® Arria® 10 Devices 2.7.5. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.6. Clock Requirements for 40GBASE-KR4 Variations 2.7.7. External TX MAC PLL 2.7.8. Placement Settings for the LL 40GbE Core
2.8. IP Core Testbenches x
2.8.1. Testbench Behavior 2.8.2. Simulating the LL 40GbE IP Core With the Testbenches
2.8.2. Simulating the LL 40GbE IP Core With the Testbenches x
2.8.2.1. Generating the LL 40GbE Testbench 2.8.2.2. Optimizing the IP Core Simulation With the Testbenches 2.8.2.3. Optimization in the 40GBASE-KR4 Testbench 2.8.2.4. Simulating with the Modelsim Simulator 2.8.2.5. Simulating with the NCSim Simulator 2.8.2.6. Simulating with the VCS Simulator 2.8.2.7. Testbench Output Example
3. Functional Description x
3.1. High Level System Overview 3.2. LL 40GbE IP Core Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. LL 40GbE IP Core Functional Description x
3.2.1. LL 40GbE IP Core TX Datapath 3.2.2. LL 40GbE IP Core TX Data Bus Interfaces 3.2.3. LL 40GbE IP Core RX Datapath 3.2.4. LL 40GbE IP Core RX Data Bus Interfaces 3.2.5. External Reconfiguration Controller 3.2.6. External Transceiver PLL 3.2.7. External TX MAC PLL 3.2.8. Congestion and Flow Control Using Pause Frames 3.2.9. Pause Control and Generation Interface 3.2.10. Pause Control Frame Filtering 3.2.11. Link Fault Signaling Interface 3.2.12. Statistics Counters Interface 3.2.13. 1588 Precision Time Protocol Interfaces 3.2.14. PHY Status Interface 3.2.15. Transceiver PHY Serial Data Interface 3.2.16. Low Latency 40GBASE-KR4 IP Core Variations 3.2.17. Control and Status Interface 3.2.18. Arria 10 Transceiver Reconfiguration Interface 3.2.19. Clocks 3.2.20. Resets
3.2.1. LL 40GbE IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter-Packet Gap Generation and Insertion 3.2.1.7. Error Insertion Test and Debug Feature
3.2.2. LL 40GbE IP Core TX Data Bus Interfaces x
3.2.2.1. LL 40GbE IP Core User Interface Data Bus 3.2.2.2. LL 40GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. LL 40GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. Order of Transmission
3.2.3. LL 40GbE IP Core RX Datapath x
3.2.3.1. LL 40GbE IP Core RX Filtering 3.2.3.2. LL 40GbE IP Core Preamble Processing 3.2.3.3. IP Core Strict SFD Checking 3.2.3.4. LL 40GbE IP Core FCS (CRC-32) Removal 3.2.3.5. LL 40GbE IP Core CRC Checking 3.2.3.6. LL 40GbE IP Core Malformed Packet Handling 3.2.3.7. RX CRC Forwarding 3.2.3.8. Inter-Packet Gap 3.2.3.9. Pause Ignore 3.2.3.10. Control Frame Identification
3.2.4. LL 40GbE IP Core RX Data Bus Interfaces x
3.2.4.1. LL 40GbE IP Core User Interface Data Bus 3.2.4.2. LL 40GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. LL 40GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.8. Congestion and Flow Control Using Pause Frames x
3.2.8.1. Conditions Triggering XOFF Frame Transmission 3.2.8.2. Conditions Triggering XON Frame Transmission
3.2.12. Statistics Counters Interface x
3.2.12.1. OctetOK Count Interface
3.2.13. 1588 Precision Time Protocol Interfaces x
3.2.13.1. Implementing a 1588 System That Includes a LL 40GbE Core 3.2.13.2. PTP Receive Functionality 3.2.13.3. PTP Transmit Functionality 3.2.13.4. External Time-of-Day Module for 1588 PTP Variations 3.2.13.5. PTP Timestamp and TOD Formats 3.2.13.6. 1588 PTP Interface Signals
3.3. Signals x
3.3.1. LL 40GbE IP Core Signals
3.4. Software Interface: Registers x
3.4.1. LL 40GbE IP Core Registers 3.4.2. LL 40GbE Hardware Design Example Registers
3.4.1. LL 40GbE IP Core Registers x
3.4.1.1. PHY Registers 3.4.1.2. Link Fault Signaling Registers 3.4.1.3. LL 40GBASE-KR4 Registers 3.4.1.4. LL 40GbE IP Core MAC Configuration Registers 3.4.1.5. Pause Registers 3.4.1.6. TX Statistics Registers 3.4.1.7. RX Statistics Registers 3.4.1.8. 1588 PTP Registers
3.4.2. LL 40GbE Hardware Design Example Registers x
3.4.2.1. Packet Client Registers
4. Debugging the Link x
4.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy
A. Arria 10 10GBASE-KR Registers x
A.1. 10GBASE-KR PHY Register Definitions
B. Additional Information x
B.1. LL 40GbE IP Core User Guide Archives B.2. LL 40GbE IP Core User Guide Revision History
1. About the LL 40GbE IP Core
2. Getting Started
3. Functional Description
4. Debugging the Link
A. Arria 10 10GBASE-KR Registers
B. Additional Information

3.2.18. Arria 10 Transceiver Reconfiguration Interface

Arria 10 variations provide a dedicated Avalon-MM interface, called the Arria 10 transceiver reconfiguration interface, to access the transceiver registers. You access the Arria 10 Native PHY IP core registers through this dedicated interface and not through the IP core general purpose control and status interface.

The Avalon-MM interface implements a standard memory-mapped protocol. You can connect an embedded processor or JTAG Avalon master to this bus to access the registers of the embedded Arria 10 Native PHY IP core.

Table 28.  Avalon-MM Arria 10 Reconfiguration Interface SignalsThe reconfig_clk clocks the signals on the LL 40GbE IP core Arria 10 transceiver reconfiguration interface. The synchronous reconfig_reset reset signal resets the interface.

Signal Name

Direction

Description

reconfig_address [11:0]

Input

Address for reads and writes

reconfig_read

Input

Read command

reconfig_write

Input

Write command

reconfig_writedata [31:0]

Input

Data to be written

reconfig_readdata [31:0]

Output

Read data

reconfig_waitrequest

Output

Interface busy signal

The Arria 10 reconfiguration interface is designed to operate at a low frequency, 100 MHz to 125 MHz, so that the user's Arria 10 transceiver reconfiguration logic does not compete for resources with the surrounding high speed datapath.

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