Low Latency 40-Gbps Ethernet IP Core User Guide

Download PDF
ID 683745
Date 3/08/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the LL 40GbE IP Core 2. Getting Started 3. Functional Description 4. Debugging the Link A. Arria 10 10GBASE-KR Registers B. Additional Information
1. About the LL 40GbE IP Core x
1.1. LL 40GbE IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. LL 40GbE IP Core Device Family Support 1.2.2. LL 40GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Arria 10 Resource Utilization 1.4.2. Stratix V Resource Utilization
2. Getting Started x
2.1. Installation and Licensing for LL 40GbE IP Core for Stratix® V Devices 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options 2.4. IP Core Parameters 2.5. Files Generated for Stratix V Variations 2.6. Files Generated for Arria 10 Variations 2.7. Integrating Your IP Core in Your Design 2.8. IP Core Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.2. Installing and Licensing Intel® FPGA IP Cores x
2.2.1. Intel® FPGA IP Evaluation Mode
2.7. Integrating Your IP Core in Your Design x
2.7.1. Pin Assignments 2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.7.3. Transceiver PLL Required in Arria 10 Designs 2.7.4. Handling Potential Jitter in Intel® Arria® 10 Devices 2.7.5. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.6. Clock Requirements for 40GBASE-KR4 Variations 2.7.7. External TX MAC PLL 2.7.8. Placement Settings for the LL 40GbE Core
2.8. IP Core Testbenches x
2.8.1. Testbench Behavior 2.8.2. Simulating the LL 40GbE IP Core With the Testbenches
2.8.2. Simulating the LL 40GbE IP Core With the Testbenches x
2.8.2.1. Generating the LL 40GbE Testbench 2.8.2.2. Optimizing the IP Core Simulation With the Testbenches 2.8.2.3. Optimization in the 40GBASE-KR4 Testbench 2.8.2.4. Simulating with the Modelsim Simulator 2.8.2.5. Simulating with the NCSim Simulator 2.8.2.6. Simulating with the VCS Simulator 2.8.2.7. Testbench Output Example
3. Functional Description x
3.1. High Level System Overview 3.2. LL 40GbE IP Core Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. LL 40GbE IP Core Functional Description x
3.2.1. LL 40GbE IP Core TX Datapath 3.2.2. LL 40GbE IP Core TX Data Bus Interfaces 3.2.3. LL 40GbE IP Core RX Datapath 3.2.4. LL 40GbE IP Core RX Data Bus Interfaces 3.2.5. External Reconfiguration Controller 3.2.6. External Transceiver PLL 3.2.7. External TX MAC PLL 3.2.8. Congestion and Flow Control Using Pause Frames 3.2.9. Pause Control and Generation Interface 3.2.10. Pause Control Frame Filtering 3.2.11. Link Fault Signaling Interface 3.2.12. Statistics Counters Interface 3.2.13. 1588 Precision Time Protocol Interfaces 3.2.14. PHY Status Interface 3.2.15. Transceiver PHY Serial Data Interface 3.2.16. Low Latency 40GBASE-KR4 IP Core Variations 3.2.17. Control and Status Interface 3.2.18. Arria 10 Transceiver Reconfiguration Interface 3.2.19. Clocks 3.2.20. Resets
3.2.1. LL 40GbE IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter-Packet Gap Generation and Insertion 3.2.1.7. Error Insertion Test and Debug Feature
3.2.2. LL 40GbE IP Core TX Data Bus Interfaces x
3.2.2.1. LL 40GbE IP Core User Interface Data Bus 3.2.2.2. LL 40GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. LL 40GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. Order of Transmission
3.2.3. LL 40GbE IP Core RX Datapath x
3.2.3.1. LL 40GbE IP Core RX Filtering 3.2.3.2. LL 40GbE IP Core Preamble Processing 3.2.3.3. IP Core Strict SFD Checking 3.2.3.4. LL 40GbE IP Core FCS (CRC-32) Removal 3.2.3.5. LL 40GbE IP Core CRC Checking 3.2.3.6. LL 40GbE IP Core Malformed Packet Handling 3.2.3.7. RX CRC Forwarding 3.2.3.8. Inter-Packet Gap 3.2.3.9. Pause Ignore 3.2.3.10. Control Frame Identification
3.2.4. LL 40GbE IP Core RX Data Bus Interfaces x
3.2.4.1. LL 40GbE IP Core User Interface Data Bus 3.2.4.2. LL 40GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. LL 40GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.8. Congestion and Flow Control Using Pause Frames x
3.2.8.1. Conditions Triggering XOFF Frame Transmission 3.2.8.2. Conditions Triggering XON Frame Transmission
3.2.12. Statistics Counters Interface x
3.2.12.1. OctetOK Count Interface
3.2.13. 1588 Precision Time Protocol Interfaces x
3.2.13.1. Implementing a 1588 System That Includes a LL 40GbE Core 3.2.13.2. PTP Receive Functionality 3.2.13.3. PTP Transmit Functionality 3.2.13.4. External Time-of-Day Module for 1588 PTP Variations 3.2.13.5. PTP Timestamp and TOD Formats 3.2.13.6. 1588 PTP Interface Signals
3.3. Signals x
3.3.1. LL 40GbE IP Core Signals
3.4. Software Interface: Registers x
3.4.1. LL 40GbE IP Core Registers 3.4.2. LL 40GbE Hardware Design Example Registers
3.4.1. LL 40GbE IP Core Registers x
3.4.1.1. PHY Registers 3.4.1.2. Link Fault Signaling Registers 3.4.1.3. LL 40GBASE-KR4 Registers 3.4.1.4. LL 40GbE IP Core MAC Configuration Registers 3.4.1.5. Pause Registers 3.4.1.6. TX Statistics Registers 3.4.1.7. RX Statistics Registers 3.4.1.8. 1588 PTP Registers
3.4.2. LL 40GbE Hardware Design Example Registers x
3.4.2.1. Packet Client Registers
4. Debugging the Link x
4.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy
A. Arria 10 10GBASE-KR Registers x
A.1. 10GBASE-KR PHY Register Definitions
B. Additional Information x
B.1. LL 40GbE IP Core User Guide Archives B.2. LL 40GbE IP Core User Guide Revision History
1. About the LL 40GbE IP Core
2. Getting Started
3. Functional Description
4. Debugging the Link
A. Arria 10 10GBASE-KR Registers
B. Additional Information

3.4.1.7. RX Statistics Registers

The RX statistics registers count RX Ethernet traffic and errors. The 64-bit statistics registers are designed to roll over, to ensure timing closure on the FPGA. However, these registers should never roll over if the link is functioning properly. The statistics registers check the size of frames, which includes the following fields:

  • Size of the destination address
  • Size of the source address
  • Size of the data
  • Four bytes of CRC

The RX statistics counters module is a synthesis option. The statistics registers are counters that are implemented inside the CSR. When you turn on the Enable RX statistics parameter in the LL 40GbE parameter editor, the counters are implemented in the CSR. When you turn off the Enable RX statistics parameter in the LL 40GbE parameter editor, the counters are not implemented in the CSR, and read access to the counters returns read data equal to 0.

Reading the value of a statistics register does not affect its value. A configuration register at offset 0x945 allows you to clear all of the RX statistics counters.

To ensure that the counters you read are consistent, you should issue a shadow request to create a snapshot of all of the RX statistics registers, by setting bit [2] of the configuration register at offset 0x945. Until you reset this bit, the counters continue to increment but the readable values remain constant.

Table 45.  Receive Side Statistics Registers

Address

Name-

Description

Access

0x900

CNTR_RX_FRAGMENTS_LO

Number of received frames less than 64 bytes and reporting a CRC error (lower 32 bits)

RO

0x901

CNTR_RX_FRAGMENTS_HI

Number of received frames less than 64 bytes and reporting a CRC error (upper 32 bits)

RO

0x902

CNTR_RX_JABBERS_LO

Number of received oversized frames reporting a CRC error (lower 32 bits)

RO

0x903

CNTR_RX_JABBERS_HI

Number of received oversized frames reporting a CRC error (upper 32 bits)

RO

0x904

CNTR_RX_FCS_LO

Number of received packets with FCS errors. This register maintains a count of the number of pulses on the l<n>_rx_fcs_error or rx_fcs_error output signal (lower 32 bits)

RO

0x905

CNTR_RX_FCS_HI

Number of received packets with FCS errors. This register maintains a count of the number of pulses on the l<n>_rx_fcs_error output signal (upper 32 bits)

RO

0x906

CNTR_RX_CRCERR_LO

Number of received frames with a frame of length at least 64, with CRC error (lower 32 bits)

RO

0x907

CNTR_RX_CRCERR_HI

Number of received frames with a frame of length at least 64, with CRC error (upper 32 bits)

RO

0x908

CNTR_RX_MCAST_DATA_ERR_LO

Number of errored multicast frames received, excluding control frames (lower 32 bits)

RO

0x909

CNTR_RX_MCAST_DATA_ERR_HI

Number of errored multicast frames received, excluding control frames (upper 32 bits)

RO

0x90A

CNTR_RX_BCAST_DATA_ERR_LO

Number of errored broadcast frames received, excluding control frames (lower 32 bits)

RO

0x90B

CNTR_RX_BCAST_DATA_ERR_HI

Number of errored broadcast frames received, excluding control frames (upper 32 bits)

RO

0x90C

CNTR_RX_UCAST_DATA_ERR_LO

Number of errored unicast frames received, excluding control frames (lower 32 bits)

RO

0x90D

CNTR_RX_UCAST_DATA_ERR_HI

Number of errored unicast frames received, excluding control frames (upper 32 bits)

RO

0x90E

CNTR_RX_MCAST_CTRL_ERR_LO

Number of errored multicast control frames received (lower 32 bits)

RO

0x90F

CNTR_RX_MCAST_CTRL_ERR_HI

Number of errored multicast control frames received (upper 32 bits)

RO

0x910

CNTR_RX_BCAST_CTRL_ERR_LO

Number of errored broadcast control frames received (lower 32 bits)

RO

0x911

CNTR_RX_BCAST_CTRL_ERR_HI

Number of errored broadcast control frames received (upper 32 bits)

RO

0x912

CNTR_RX_UCAST_CTRL_ERR_LO

Number of errored unicast control frames received (lower 32 bits)

RO

0x913

CNTR_RX_UCAST_CTRL_ERR_HI

Number of errored unicast control frames received (upper 32 bits)

RO

0x914

CNTR_RX_PAUSE_ERR_LO

Number of errored pause frames received (lower 32 bits)

RO

0x915

CNTR_RX_PAUSE_ERR_HI

Number of errored pause frames received (upper 32 bits)

RO

0x916

CNTR_RX_64B_LO

Number of 64-byte received frames (lower 32 bits), including the CRC field but excluding the preamble and SFD bytes

RO

0x917

CNTR_RX_64B_HI

Number of 64-byte received frames (upper 32 bits), including the CRC field but excluding the preamble and SFD bytes

RO

0x918

CNTR_RX_65to127B_LO

Number of received frames between 65–127 bytes (lower 32 bits)

RO

0x919

CNTR_RX_65to127B_HI

Number of received frames between 65–127 bytes (upper 32 bits)

RO

0x91A

CNTR_RX_128to255B_LO

Number of received frames between 128 –255 bytes (lower 32 bits)

RO

0x91B

CNTR_RX_128to255B_HI

Number of received frames between 128 –255 bytes (upper 32 bits)

RO

0x91C

CNTR_RX_256to511B_LO

Number of received frames between 256 –511 bytes (lower 32 bits)

RO

0x91D

CNTR_RX_256to511B_HI

Number of received frames between 256 –511 bytes (upper 32 bits)

RO

0x91E

CNTR_RX_512to1023B_LO

Number of received frames between 512–1023 bytes (lower 32 bits)

RO

0x91F

CNTR_RX_512to1023B_HI

Number of received frames between 512 –1023 bytes (upper 32 bits)

RO

0x920

CNTR_RX_1024to1518B_LO

Number of received frames between 1024–1518 bytes (lower 32 bits)

RO

0x921

CNTR_RX_1024to1518B_HI

Number of received frames between 1024–1518 bytes (upper 32 bits)

RO

0x922

CNTR_RX_1519toMAXB_LO

Number of received frames between 1519 bytes and the maximum size defined in the MAX_RX_SIZE_CONFIG register (lower 32 bits)

RO

0x923

CNTR_RX_1519toMAXB_HI

Number of received frames between 1519 bytes and the maximum size defined in the MAX_RX_SIZE_CONFIG register (upper 32 bits)

RO

0x924

CNTR_RX_OVERSIZE_LO

Number of oversized frames (frames with more bytes than the number specified in the MAX_RX_SIZE_CONFIG register) received (lower 32 bits)

RO

0x925

CNTR_RX_OVERSIZE_HI

Number of oversized frames (frames with more bytes than the number specified in the MAX_RX_SIZE_CONFIG register) received (upper 32 bits)

RO

0x926

CNTR_RX_MCAST_DATA_OK_LO

Number of valid multicast frames received, excluding control frames (lower 32 bits)

RO

0x927

CNTR_RX_MCAST_DATA_OK_HI

Number of valid multicast frames received, excluding control frames (upper 32 bits)

RO

0x928

CNTR_RX_BCAST_DATA_OK_LO

Number of valid broadcast frames received, excluding control frames (lower 32 bits)

RO

0x929

CNTR_RX_BCAST_DATA_OK_HI

Number of valid broadcast frames received, excluding control frames (upper 32 bits)

RO

0x92A

CNTR_RX_UCAST_DATA_OK_LO

Number of valid unicast frames received, excluding control frames (lower 32 bits)

RO

0x92B

CNTR_RX_UCAST_DATA_OK_HI

Number of valid unicast frames received, excluding control frames (upper 32 bits)

RO

0x92C

CNTR_RX_MCAST_CTRL_LO

Number of valid multicast frames received, excluding data frames (lower 32 bits)

RO

0x92D

CNTR_RX_MCAST_CTRL_HI

Number of valid multicast frames received, excluding data frames (upper 32 bits)

RO

0x92E

CNTR_RX_BCAST_CTRL_LO

Number of valid broadcast frames received, excluding data frames (lower 32 bits)

RO

0x92F

CNTR_RX_BCAST_CTRL_HI

Number of valid broadcast frames received, excluding data frames (upper 32 bits)

RO

0x930

CNTR_RX_UCAST_CTRL_LO

Number of valid unicast frames received, excluding data frames (lower 32 bits)

RO

0x931

CNTR_RX_UCAST_CTRL_HI

Number of valid unicast frames received, excluding data frames (upper 32 bits)

RO

0x932

CNTR_RX_PAUSE_LO

Number of valid pause frames received (lower 32 bits)

RO

0x933

CNTR_RX_PAUSE_HI

Number of valid pause frames received (upper 32 bits)

RO

0x934

CNTR_RX_RUNT_LO

Number of received runt packets (lower 32 bits)

A run is a packet of size less than 64 bytes but greater than eight bytes. If a packet is eight bytes or smaller, it is considered a decoding error and not a runt frame, and the IP core does not flag it nor count it as a runt.

RO

0x935

CNTR_RX_RUNT_HI

Number of received runt packets (upper 32 bits)

A run is a packet of size less than 64 bytes but greater than eight bytes. If a packet is eight bytes or smaller, it is considered a decoding error and not a runt frame, and the IP core does not flag it nor count it as a runt.

RO

0x936

CNTR_RX_ST_LO

Number of received frame starts (lower 32 bits)

RO

0x937

CNTR_RX_ST_HI

Number of received frame starts (upper 32 bits)

RO

0x938–0x93F

Reserved

0x940 RXSTAT_REVID RX statistics module revision ID. RO
0x941 RXSTAT_SCRATCH Scratch register available for testing. Default value is 0x09. RW
0x942 RXSTAT_NAME_0 First 4 characters of IP core variation identifier string "040gMacStats" RO
0x943 RXSTAT_NAME_1 Next 4 characters of IP core variation identifier string "040gMacStats" RO
0x944 RXSTAT_NAME_2 Final 4 characters of IP core variation identifier string "040gMacStats" RO
0x945

CNTR_RX_CONFIG

Bits [2:0]: Configuration of RX statistics counters:

  • Bit [2]: Shadow request (active high): When set to the value of 1, RX statistics collection is paused. The underlying counters continue to operate, but the readable values reflect a snapshot at the time the pause flag was activated. Write a 0 to release.
  • Bit [1]: Parity-error clear. When software sets this bit, the IP core clears the parity bit CNTR_RX_STATUS[0]. This bit (CNTR_RX_CONFIG[1]) is self-clearing.
  • Bit [0]: Software can set this bit to the value of 1 to reset all of the RX statistics registers at the same time. This bit is self-clearing.

Bits [31:3] are Reserved.

RW

0x946

CNTR_RX_STATUS

  • Bit [1]: Indicates that the RX statistics registers are paused (while CNTR_RX_CONFIG[2] is asserted) .
  • Bit [0]: Indicates the presence of at least one parity error in the RX statistics counters.

Bits [31:2] are Reserved.

RO
0x960 RxOctetsOK_LO Number of received payload bytes in frames with no FCS, undersized, oversized, or payload length errors. This register is compliant with section 5.2.1.14 of the IEEE Standard 802.3-2008.

This register corresponds to the signals rx_inc_octetsOK[15:0] and rx_inc_octetsOK_valid.

RO
0x961 RxOctetsOK_HI RO
Related Information
Level Two Title