Low Latency 40-Gbps Ethernet IP Core User Guide

ID 683745
Date 3/08/2021
Document Table of Contents

1.4.1. Arria 10 Resource Utilization

Resource utilization changes depending on the parameter settings you specify in the LL 40GbE parameter editor. For example, if you turn on pause functionality or statistics counters in the LL 40GbE parameter editor, the IP core requires additional resources to implement the additional functionality.

Table 5.  IP Core FPGA Resource Utilization in Arria 10 Devices Lists the resources and expected performance for selected variations of the LL 40GbE IP core in an Arria 10 device.

These results were obtained using the Intel® Quartus® Prime software v14.1 .

  • The numbers of ALMs and logic registers are rounded up to the nearest 100.
  • The numbers of ALMs, before rounding, are the ALMs needed numbers from the Intel® Quartus® Prime Fitter Report.

LL 40GbE Variation


Dedicated Logic Registers



LL 40GbE variation A

5400 12800 13

LL 40GbE variation B

10100 21200 13
LL 40GbE variation C 11000 24100 13

LL 40GbE variation D

14200 31100 17

LL 40GbE variation E

14400 28200 26
LL 40GbE variation F 16300 29300 26