Low Latency 40-Gbps Ethernet IP Core User Guide

ID 683745
Date 3/08/2021
Document Table of Contents

2.7.5. External Time-of-Day Module for Variations with 1588 PTP Feature

LL 40GbE IP cores that include the 1588 PTP module require an external time-of-day (TOD) module to provide a continuous flow of current time-of-day information. The TOD module must update the time-of-day output value on every clock cycle, and must provide the TOD value in the V2 format (96 bits) or the 64-bit TOD format, or both.

The example project you can generate for your IP core PTP variation includes a TOD module, implemented as two distinct, simple TOD modules, one connected to the TX MAC and one connected to the RX MAC.

Table 15.  TOD Module Required ConnectionsRequired connections for TOD module, listed using signal names for TOD modules that provide both a 96-bit TOD and a 64-bit TOD. If you create your own TOD module it must have the output signals required by the LL 40GbE IP core. However, its signal names could be different than the TOD module signal names in the table. The signals that that the IP core includes depend on the Enable 96b Time of Day Format and Enable 64b Time of Day Format parameters. For example, an RX TOD module might require only a 96-bit TOD out signal.
TOD Module Signal LL 40GbE IP Core Signal
rst_txmac (input) Drive this signal from the same source as the reset_async input signal to the LL 40GbE IP core.
rst_rxmac (input) Drive this signal from the same source as the reset_async input signal to the LL 40GbE IP core.
tod_txmclk_96b[95:0] (output) tx_time_of_day_96b_data[95:0] (input)
tod_txmclk_64b[63:0] (output) tx_time_of_day_64b_data[63:0] (input)
tod_rxmclk_96b[95:0] (output) rx_time_of_day_96b_data[95:0] (input)
tod_rxmclk_64b[63:0] (output) rx_time_of_day_64b_data[63:0] (input)
clk_txmac (input) clk_txmac (output)
clk_rxmac (input) clk_rxmac (output)

Did you find the information on this page useful?

Characters remaining:

Feedback Message