Low Latency 40-Gbps Ethernet IP Core User Guide

ID 683745
Date 3/08/2021
Document Table of Contents

2.7.6. Clock Requirements for 40GBASE-KR4 Variations

In 40GBASE-KR4 IP core designs, you must drive the clocks for the two IP core register interfaces (reconfig_clk and clk_status) from the same clock source.

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