2.7.7. External TX MAC PLL
If you turn on Use external TX MAC PLL in the LL 40GbE parameter editor, you must connect the clk_txmac_in input port to a clock source, usually a PLL on the device.
The clk_txmac_in signal drives the clk_txmac clock in the IP core TX MAC and PHY. If you turn off this parameter, the clk_txmac_in input clock signal is not available.
The required TX MAC clock frequency is 312.5 MHz . User logic must drive clk_txmac_in from a PLL whose input is the PHY reference clock, clk_ref.
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