Low Latency 40-Gbps Ethernet IP Core User Guide

ID 683745
Date 3/08/2021
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3.2.7. External TX MAC PLL

If you turn on Use external TX MAC PLL in the LL 40GbE parameter editor, the IP core has an extra input port, clk_txmac_in, which drives the TX MAC clock. You must connect this input port to a clock source, usually a PLL on the device.

The port is expected to receive the clock from the external TX MAC PLL and drives the internal clock clk_txmac. The required TX MAC clock frequency is 312.5 MHz . User logic must drive clk_txmac_in from a PLL whose input is the PHY reference clock, clk_ref.