Low Latency 40-Gbps Ethernet IP Core User Guide

Download PDF
ID 683745
Date 3/08/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the LL 40GbE IP Core 2. Getting Started 3. Functional Description 4. Debugging the Link A. Arria 10 10GBASE-KR Registers B. Additional Information
1. About the LL 40GbE IP Core x
1.1. LL 40GbE IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. LL 40GbE IP Core Device Family Support 1.2.2. LL 40GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Arria 10 Resource Utilization 1.4.2. Stratix V Resource Utilization
2. Getting Started x
2.1. Installation and Licensing for LL 40GbE IP Core for Stratix® V Devices 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options 2.4. IP Core Parameters 2.5. Files Generated for Stratix V Variations 2.6. Files Generated for Arria 10 Variations 2.7. Integrating Your IP Core in Your Design 2.8. IP Core Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.2. Installing and Licensing Intel® FPGA IP Cores x
2.2.1. Intel® FPGA IP Evaluation Mode
2.7. Integrating Your IP Core in Your Design x
2.7.1. Pin Assignments 2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.7.3. Transceiver PLL Required in Arria 10 Designs 2.7.4. Handling Potential Jitter in Intel® Arria® 10 Devices 2.7.5. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.6. Clock Requirements for 40GBASE-KR4 Variations 2.7.7. External TX MAC PLL 2.7.8. Placement Settings for the LL 40GbE Core
2.8. IP Core Testbenches x
2.8.1. Testbench Behavior 2.8.2. Simulating the LL 40GbE IP Core With the Testbenches
2.8.2. Simulating the LL 40GbE IP Core With the Testbenches x
2.8.2.1. Generating the LL 40GbE Testbench 2.8.2.2. Optimizing the IP Core Simulation With the Testbenches 2.8.2.3. Optimization in the 40GBASE-KR4 Testbench 2.8.2.4. Simulating with the Modelsim Simulator 2.8.2.5. Simulating with the NCSim Simulator 2.8.2.6. Simulating with the VCS Simulator 2.8.2.7. Testbench Output Example
3. Functional Description x
3.1. High Level System Overview 3.2. LL 40GbE IP Core Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. LL 40GbE IP Core Functional Description x
3.2.1. LL 40GbE IP Core TX Datapath 3.2.2. LL 40GbE IP Core TX Data Bus Interfaces 3.2.3. LL 40GbE IP Core RX Datapath 3.2.4. LL 40GbE IP Core RX Data Bus Interfaces 3.2.5. External Reconfiguration Controller 3.2.6. External Transceiver PLL 3.2.7. External TX MAC PLL 3.2.8. Congestion and Flow Control Using Pause Frames 3.2.9. Pause Control and Generation Interface 3.2.10. Pause Control Frame Filtering 3.2.11. Link Fault Signaling Interface 3.2.12. Statistics Counters Interface 3.2.13. 1588 Precision Time Protocol Interfaces 3.2.14. PHY Status Interface 3.2.15. Transceiver PHY Serial Data Interface 3.2.16. Low Latency 40GBASE-KR4 IP Core Variations 3.2.17. Control and Status Interface 3.2.18. Arria 10 Transceiver Reconfiguration Interface 3.2.19. Clocks 3.2.20. Resets
3.2.1. LL 40GbE IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter-Packet Gap Generation and Insertion 3.2.1.7. Error Insertion Test and Debug Feature
3.2.2. LL 40GbE IP Core TX Data Bus Interfaces x
3.2.2.1. LL 40GbE IP Core User Interface Data Bus 3.2.2.2. LL 40GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. LL 40GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. Order of Transmission
3.2.3. LL 40GbE IP Core RX Datapath x
3.2.3.1. LL 40GbE IP Core RX Filtering 3.2.3.2. LL 40GbE IP Core Preamble Processing 3.2.3.3. IP Core Strict SFD Checking 3.2.3.4. LL 40GbE IP Core FCS (CRC-32) Removal 3.2.3.5. LL 40GbE IP Core CRC Checking 3.2.3.6. LL 40GbE IP Core Malformed Packet Handling 3.2.3.7. RX CRC Forwarding 3.2.3.8. Inter-Packet Gap 3.2.3.9. Pause Ignore 3.2.3.10. Control Frame Identification
3.2.4. LL 40GbE IP Core RX Data Bus Interfaces x
3.2.4.1. LL 40GbE IP Core User Interface Data Bus 3.2.4.2. LL 40GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. LL 40GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.8. Congestion and Flow Control Using Pause Frames x
3.2.8.1. Conditions Triggering XOFF Frame Transmission 3.2.8.2. Conditions Triggering XON Frame Transmission
3.2.12. Statistics Counters Interface x
3.2.12.1. OctetOK Count Interface
3.2.13. 1588 Precision Time Protocol Interfaces x
3.2.13.1. Implementing a 1588 System That Includes a LL 40GbE Core 3.2.13.2. PTP Receive Functionality 3.2.13.3. PTP Transmit Functionality 3.2.13.4. External Time-of-Day Module for 1588 PTP Variations 3.2.13.5. PTP Timestamp and TOD Formats 3.2.13.6. 1588 PTP Interface Signals
3.3. Signals x
3.3.1. LL 40GbE IP Core Signals
3.4. Software Interface: Registers x
3.4.1. LL 40GbE IP Core Registers 3.4.2. LL 40GbE Hardware Design Example Registers
3.4.1. LL 40GbE IP Core Registers x
3.4.1.1. PHY Registers 3.4.1.2. Link Fault Signaling Registers 3.4.1.3. LL 40GBASE-KR4 Registers 3.4.1.4. LL 40GbE IP Core MAC Configuration Registers 3.4.1.5. Pause Registers 3.4.1.6. TX Statistics Registers 3.4.1.7. RX Statistics Registers 3.4.1.8. 1588 PTP Registers
3.4.2. LL 40GbE Hardware Design Example Registers x
3.4.2.1. Packet Client Registers
4. Debugging the Link x
4.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy
A. Arria 10 10GBASE-KR Registers x
A.1. 10GBASE-KR PHY Register Definitions
B. Additional Information x
B.1. LL 40GbE IP Core User Guide Archives B.2. LL 40GbE IP Core User Guide Revision History
1. About the LL 40GbE IP Core
2. Getting Started
3. Functional Description
4. Debugging the Link
A. Arria 10 10GBASE-KR Registers
B. Additional Information

3.2.16. Low Latency 40GBASE-KR4 IP Core Variations

The LL 40GBASE-KR4 IP core supports low-level control of analog transceiver properties for link training and auto-negotiation in the absence of a predetermined environment for the IP core. For example, an Ethernet IP core in a backplane may have to communicate with different link partners at different times. When it powers up, the environment parameters may be different than when it ran previously. The environment can also change dynamically, necessitating reset and renegotiation of the Ethernet link.

The LL 40GbE IP core 40GBASE-KR4 variations implement the IEEE Backplane Ethernet Standard 802.3ap-2007 . The LL 40GbE IP core provides this reconfiguration functionality in Arria 10 devices by configuring each physical Ethernet lane with an Intel Backplane Ethernet 10GBASE-KR PHY IP core if you turn on Enable KR4 in the LL 40GbE parameter editor. The parameter is available in variations parameterized with these values:

  • Device family: Arria 10
  • Protocol speed: 40GbE
  • Enable 1588 PTP : Off

The IP core includes the option to implement the following features:

  • KR auto-negotiation provides a process to explore coordination with a link partner on a variety of different common features. The 40GBASE-KR4 variations of the LL 40GbE IP core can auto-negotiate only to a 40GBASE-KR4 configuration. Turn on the Enable KR4 Reconfiguration and Enable Auto-Negotiation parameters to configure support for auto-negotiation.

  • Link training provides a process for the IP core to train the link to the data frequency of incoming data, while compensating for variations in process, voltage, and temperature. Turn on the Enable KR4 Reconfiguration and Enable Link Training parameters to configure support for link training.

  • After the link is up and running, forward error correction (FEC) provides an error detection and correction mechanism to enable noisy channels to achieve the Ethernet-mandated bit error rate (BER) of 10-12. Turn on the Include FEC sublayer parameter to configure support for FEC.

The LL 40GBASE-KR4 IP core variations include separate link training and FEC modules for each of the four Ethernet lanes, and a single auto-negotiation module. You specify the master lane for performing auto-negotiation in the parameter editor, and the IP core also provides register support to modify the selection dynamically.

Intel provides a testbench for LL 40GBASE-KR4 IP core variations with an Avalon-ST client interface that generate their own TX MAC clock (Use external TX MAC PLL is turned off). Intel provides a hardware design example for all LL 40GBASE-KR4 IP core variations that generate their own TX MAC clock, to assist you in integrating your LL 40GBASE-KR4 IP core into your complete design. You can examine the design example for an example of how to drive and connect the 40GBASE-KR4 IP core.

IP core FEC functionality relies on register settings in the LL 40GBASE-KR4 registers and on some specific register fields in the Arria 10 device registers.

To simulate correctly and to run correctly in hardware, you must drive the reconfig_clk and the clk_status inputs from the same source clock.

Related Information
Level Two Title