PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 8/02/2023
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5.4. I/O Standards

The PHY Lite for Parallel Interfaces IP allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups.

Table 105.  I/O Standards and Termination Values for Intel® Arria® 10 Devices
I/O Standard Valid Input Terminations (Ω) 13 Valid Output Calibrated/Uncalibrated Terminations (Ω)13 RZQ (Ω) 14 Differential/Complementary I/O Support
SSTL-12 15 60, 120 40, 60 240 Yes
SSTL-125 15 60, 120 34, 40 240 Yes
SSTL-135 15 60, 120 34, 40 240 Yes
SSTL-15 15 60, 120 34, 40 240 Yes
SSTL-15 Class I 16 0, 50 0, 50 100 Yes
SSTL-15 Class II16 0, 50 0, 25 100 Yes
SSTL-18 Class I16 0, 50 0, 50 100 Yes
SSTL-18 Class II16 0, 50 0, 25 100 Yes
1.2-V HSTL Class I16 0, 50 0, 50 100 Yes
1.2-V HSTL Class II16 0, 50 0, 25 100 Yes
1.5-V HSTL Class I16 0, 50 0, 50 100 Yes
1.5-V HSTL Class II16 0, 50 0, 25 100 Yes
1.8-V HSTL Class I16 0, 50 0, 50 100 Yes
1.8-V HSTL Class II16 0, 50 0, 25 100 Yes
1.2-V POD 34, 40, 48, 60, 80, 120, 240 34, 40, 48, 60 240 Yes
1.2-V No
1.5-V No
1.8-V No
Table 106.  I/O Standards and Termination Values for Intel® Cyclone® 10 GX Devices
I/O Standard Valid Input Terminations (Ω) 13 Valid Output Calibrated/Uncalibrated Terminations (Ω)13 RZQ (Ω) 14 Differential/Complementary I/O Support
SSTL-12 17 60, 120 40, 60 240 Yes
SSTL-125 17 60, 120 34, 40 240 Yes
SSTL-135 17 60, 120 34, 40 240 Yes
SSTL-15 17 60, 120 34, 40 240 Yes
SSTL-15 Class I 18 0, 50 0, 50 100 Yes
SSTL-15 Class II18 0, 50 0, 25 100 Yes
SSTL-18 Class I18 0, 50 0, 50 100 Yes
SSTL-18 Class II18 0, 50 0, 25 100 Yes
1.2-V HSTL Class I18 0, 50 0, 50 100 Yes
1.2-V HSTL Class II18 0, 50 0, 25 100 Yes
1.5-V HSTL Class I18 0, 50 0, 50 100 Yes
1.5-V HSTL Class II18 0, 50 0, 25 100 Yes
1.8-V HSTL Class I18 0, 50 0, 50 100 Yes
1.8-V HSTL Class II18 0, 50 0, 25 100 Yes
1.2-V POD 34, 40, 48, 60, 80, 120, 240 34, 40, 48, 60 240 Yes
1.2-V No
1.5-V No
1.8-V No
13 0 is equivalent to no termination.
14 RZQ pin is not required for uncalibrated output terminations.
15 Use this I/O standard if input termination is required with interface frequency more than 533 MHz.
16 Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz.
17 Use this I/O standard if input termination is required with interface frequency more than 533 MHz.
18 Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz.