PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 8/02/2023

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Document Table of Contents Generate the Simulation Design Example

The make_sim_design.tcl generates a simulation design example and tool specific scripts to compile and elaborate the necessary files.
To generate the design example for a Verilog or a mixed-language simulator, run the following script at the end of IP generation:
quartus_sh -t make_sim_design.tcl VERILOG
To generate the design example for a VHDL-only simulator, run the following script:
quartus_sh -t make_sim_design.tcl VHDL

This script generates a sim directory containing one subdirectory for each supported simulation tool. Each subdirectory contains the specific scripts to run simulation using the corresponding tool.

Figure 14. High-Level View of the Simulation Design Example with Dynamic Reconfiguration