PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
ID
683716
Date
8/02/2023
Public
A newer version of this document is available. Customers should click here to go to the newest version.
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series
3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series
4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
7. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
3.2.4.3. Dynamic Reconfiguration Guidelines
The PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP for F-Series and I-Series allows you to dynamically reconfigure the features of the interface. No traffic should occur during reconfiguration. Reframing is necessary, particularly in continuous strobe mode of operation. Intel recommends performing dynamic calibration for application with core clock frequency of more than 533 MHz. This section provides the general guidelines for calibrating Intel Agilex® 7 F-Series and I-Series I/O architecture.
Note: Follow the guidelines when generating your own dynamic reconfiguration controller.