PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 8/02/2023
Public

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2.2.2.1. Calibration IP

Calibration IP provides access to the IOPLL and PHY registers through the AXI4-Lite IP Interface. Calibration IP can be connected to up to two periphery interfaces and three PLLs.

Table 11.  AXI4-Lite IP Interface SignalsThis table describes the AXI4-Lite IP Interface signals.
Signal Name Direction Width Description
fbr_axil_clk Input 1 Clock
fbr_axil_rst_n Input 1 Reset
fbr_axil_awaddr Input 27 Write address
fbr_axil_awvalid Input 1 Write address valid
fbr_axil_awready Output 1 Write address ready
fbr_axil_wdata Input 32 Write data
fbr_axil_wstrb Input 4 Write strobes
fbr_axil_wvalid Input 1 Write valid
fbr_axil_wready Output 1 Write ready
fbr_axil_bresp Output 2 Write response
fbr_axil_bvalid Output 1 Write response valid
fbr_axil_bready Input 1 Response ready
fbr_axil_araddr Input 27 Read address
fbr_axil_arvalid Input 1 Read address valid
fbr_axil_arready Output 1 Read address ready
fbr_axil_rdata Output 32 Read data
fbr_axil_rresp Output 2 Read response
fbr_axil_rvalid Output 1 Read valid
fbr_axil_rready Input 1 Read Ready
fbr_axil_awprot Input 3 Write protection type
fbr_axil_arprot Input 3 Read protection type