PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 8/02/2023
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2.5.1.1.1. Generate the Synthesis Design Example

The make_qii_design.tcl generates a synthesizable hardware design example and an Intel® Quartus® Prime project, ready for compilation.

To generate synthesizable design example, run the following script at the end of IP generation:

quartus_sh -t make_qii_design.tcl

To specify an exact device to use, run the following script:

quartus_sh -t make_qii_design.tcl [device_name]

This script generates a qii directory containing a project called ed_synth.qpf. Use the Intel® Quartus® Prime software to open and compile this project.

Figure 11. High-Level View of the Synthesis Design Example with One Group