PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 8/02/2023
Public

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1.2. Features

The PHY Lite for Parallel Interfaces IP:

  • Supports input, output, and bidirectional data channels.
  • Supports DQS gating/ungating circuitry for strobe-based interfaces.
  • Supports output delays via interpolator.
  • Supports dynamic on-chip termination (OCT) control.
  • Supports quarter-rate, half-rate, and full-rate of the interface clock conversions.
  • Supports input, output, and read/DQS/OCT enable paths.
  • Supports single data rate (SDR) and double data rate (DDR) at the I/Os.
  • Supports PHY clock tree.
  • Supports dynamically reconfigurable delay chains using Avalon® memory-mapped interface.
  • Supports process, voltage, and temperature (PVT) or non-PVT compensated input and DQS delay chains
    Note: For Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX, the non-PVT compensated component of the input delay is set through the .qsf assignment in the Intel® Quartus® Prime software.