PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 8/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data

If the input data is not edge-aligned, use the following equation to calculate the new Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint values:

New Input Strobe Setup Delay Constraint Value = Clock to data skew - Input Strobe Phase Shift (nanosecond)

New Input Strobe Hold Delay Constraint Value = Clock to data skew + Input Strobe Phase Shift (nanosecond)

For example, if the memory speed is 800 MHz and the clock to data skew value is 0.1 with input data phase shift of 90°:

New Input Strobe Setup Delay Constraint value = 0.1-1.25*(90/360) = -0.2125ns.

New Input Strobe Hold Delay Constraint value = 0.1 + 1.25*(90/360) = 0.4125ns

Important: Ensure that you make the changes in the Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint parameters.