PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 8/02/2023
Public

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2.2.1. PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP Top Level Interfaces

The PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP consists of the following modules:

  • Clocks and reset
  • Fabric
  • PHY data and control
  • I/O
Figure 2. Top Level InterfaceThis figure shows the top-level diagram of the PHY Lite for Parallel Interfaces IP interface.