PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 8/02/2023
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5.2.3. Output Path

The output path consists of a FIFO and an interpolator.

Table 82.  Blocks in Output PathThis table lists the blocks in the output path.
Block Description
Write FIFO Serializes the output data from the core with a serialization factor of up to 8 (in DDR quarter-rate).
Interpolator Works with the FIFO block to generate the desired output delay. You can dynamically configure the delay through the Avalon memory-mapped interface. For more information, refer to Dynamic Reconfiguration section.
Figure 83. Output PathThis figure shows the output path for the PHY Lite for Parallel Interfaces IP.
The following figures show the waveform diagrams for the output path. The delays shown in the waveforms are just estimation based on simulations and these values are different with different core clock rate and VCO multiplier.
Figure 84.  Output Path ─ Write Latency 0This simulation is based on the following PHY Lite for Parallel Interfaces IP configurations:
  • Interface Frequency: 1000 MHz
  • VCO Multiplier Factor: 1
  • User logic clock rate: Quarter rate
Figure 85.  Output Path ─ Write Latency 2This simulation is based on the following PHY Lite for Parallel Interfaces IP configurations:
  • Interface Frequency: 1000 MHz
  • VCO Multiplier Factor: 1
  • User logic clock rate: Quarter rate