PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 8/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.5. Design Example

The PHY Lite for Parallel Interfaces Intel Agilex® 7 M-Series FPGA IP is able to generate a design example that matches the same configuration chosen for the IP. The design example is a simple design that does not target any specific application; however you can use the design example as a reference on how to instantiate the IP and what behavior to expect in a simulation.

You can generate a design example by clicking Generating Example Design in the IP Parameter Editor.

Note: The .qsys files are for internal use during design example generation only. You should not edit the files.