PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 8/02/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents DQS Trees

The PHY Lite for Parallel Interfaces IP support two DQS trees, namely an x8 tree that span over one lane and an x16 tree that spans over two adjacent lanes, as described in the following table:

Table 19.  DQS Trees in Intel Agilex® 7 M-Series Devices
DQS Tree Lane Used Group Size Strobe Pins
X8 Any lane 1-10 Pins 4, 5





1-22 Pins 4, 5 of the even lane

For single-ended strobe, only pin 4 is used as DQS. The remaining strobe pin (pin 5) cannot be used as data.