PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 8/02/2023
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2.5.2. Verify Simulation Design Examples using Tester IP

The design examples, both with dynamic reconfiguration and without dynamic reconfiguration, use Tester IP to verify PHY Lite for Parallel Interfaces IP functionality. The tester exercises read and write operations to the PHY Lite for Parallel Interfaces IP to verify its functionality.
At a high level, the tester is a state machine that repeatedly performs read/write operations. Disabling a test causes the corresponding tester state to be skipped. The following lists the tester states in the order they are performed:
  1. STATE_INIT: Initialization
  2. STATE_TEST_CALBUS: Calibration when dynamic reconfiguration is enabled
  3. STATE_TEST_WRITE: Enabled only in output and bidir modes
  4. STATE_TEST_READ: Enabled only in input and bidir modes
  5. STATE_DONE: All bursts of data successfully transmitted
The following table shows the port connections between the PHY Lite for Parallel Interfaces IP and tester. Tester ports not shown in the table are pass_out and fail_out which signal the success or failure of the test. Multiple PHY Lite for Parallel Interfaces IP groups can be tested by daisy chaining testers and connecting pass_out and fail_out of each tester to the pass_in and fail_in ports of the next tester in chain. The Calbus ports are not shown in the table as well.
Table 21.   PHY Lite for Parallel Interfaces IP for M-Series Devices and Tester Port ConnectionsThis table lists the PHY Lite and Tester port connections.
Ports Connection PHY Lite for Parallel Interfaces Ports Width Tester Ports
PHY Lite for Parallel Interfaces IP interface submodule group_X_data_from_core GROUP_DATA_WIDTH group_data_from_core
group_X_oe_from_core GROUP_CTRL_WIDTH group_oe_from_core
group_X_strobe_from_core GROUP_STROBE_WIDTH group_strobe_from_core
group_X_strobe_out_en GROUP_CTRL_WIDTH group_strobe_out_en
group_X_data_to_core GROUP_DATA_WIDTH group_data_to_core
group_X_rdata_en GROUP_CTRL_WIDTH group_rdata_en
group_X_rdata_valid GROUP_CTRL_WIDTH group_rdata_valid
I/O model group_X_data_out GROUP_PIN_WIDTH group_data_out
group_X_data_out_n GROUP_PIN_WIDTH group_data_out_n
group_X_data_in GROUP_PIN_WIDTH group_data_in
group_X_data_in_n GROUP_PIN_WIDTH group_data_in_n
group_X_data_io GROUP_PIN_WIDTH group_data_io
group_X_data_io_n GROUP_PIN_WIDTH group_data_io_n
group_X_strobe_out N/A group_strobe_out
group_X_strobe_out_n group_strobe_out_n
group_X_strobe_in group_strobe_in
group_X_strobe_in_n group_strobe_in_n
group_X_strobe_io group_strobe_io
group_X_strobe_io_n group_strobe_io_n
The tester instantiates the following three submodules:
  • I/O model: Connects to the PHY Lite for Parallel Interfaces I/O interface. Includes two instances of prbs channel, one to generate random pattern for read tests, and one to check the received pattern in the write tests.
  • PHY Lite for Parallel Interfaces IP interface: Connects to the PHY Lite for Parallel Interfaces IP core interface. Includes two instances of prbs channel, one to generate random pattern for write tests, and one to check received pattern in the read tests. Reframing logic is also included in this module.
  • IOSSM tester: Exposes an AXI4-Lite IP Interface and performs reads and writes to change the TX delay on pin 0. Only available for simulation example design with dynamic reconfiguration.