PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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Date 8/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the PHY Lite for Parallel Interfaces IP 2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series 3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series 4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP 5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs 6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives 7. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
1. About the PHY Lite for Parallel Interfaces IP x
1.1. Device Family Support 1.2. Features
2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series x
2.1. Release Information 2.2. Functional Description 2.3. Getting Started 2.4. I/O Standards 2.5. Design Example
2.2. Functional Description x
2.2.1. PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP Top Level Interfaces 2.2.2. Dynamic Reconfiguration
2.2.1. PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP Top Level Interfaces x
2.2.1.1. Clocks 2.2.1.2. Output Path 2.2.1.3. Input Path
2.2.1.1. Clocks x
2.2.1.1.1. Clock Frequency Relationships
2.2.2. Dynamic Reconfiguration x
2.2.2.1. Calibration IP 2.2.2.2. Dynamic Reconfigurable Delays 2.2.2.3. Register Map
2.3. Getting Started x
2.3.1. Parameter Settings 2.3.2. Signals
2.3.2. Signals x
2.3.2.1. Clock and Reset Interface Signals 2.3.2.2. Output Path Signals 2.3.2.3. Input Path Signals
2.4. I/O Standards x
2.4.1. Design Guidelines
2.4.1. Design Guidelines x
2.4.1.1. DQS Trees 2.4.1.2. Pin Placement Restrictions
2.5. Design Example x
2.5.1. Generate the Design Example 2.5.2. Verify Simulation Design Examples using Tester IP
2.5.1. Generate the Design Example x
2.5.1.1. Design Example without Dynamic Reconfiguration 2.5.1.2. Dynamic Reconfiguration Design Examples
2.5.1.1. Design Example without Dynamic Reconfiguration x
2.5.1.1.1. Generate the Synthesis Design Example 2.5.1.1.2. Generate the Simulation Design Example
2.5.1.2. Dynamic Reconfiguration Design Examples x
2.5.1.2.1. Generate the Synthesis Design Example 2.5.1.2.2. Generate the Simulation Design Example
3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series x
3.1. Release Information 3.2. Functional Description 3.3. Getting Started 3.4. I/O Standards 3.5. Design Guidelines 3.6. Design Example
3.2. Functional Description x
3.2.1. Intel Agilex® 7 F-Series and I-Series I/O Sub-bank Interconnects 3.2.2. Intel Agilex® 7 F-Series and I-Series Input DQS/Strobe Tree 3.2.3. PHY Lite for Parallel Interfaces Intel Agilex® 7 for F-Series and I-Series FPGA IP Top Level Interfaces 3.2.4. Dynamic Reconfiguration 3.2.5. I/O Timing
3.2.3. PHY Lite for Parallel Interfaces Intel Agilex® 7 for F-Series and I-Series FPGA IP Top Level Interfaces x
3.2.3.1. Clocks 3.2.3.2. Output Path 3.2.3.3. Input Path
3.2.3.1. Clocks x
3.2.3.1.1. Clock Frequency Relationships
3.2.4. Dynamic Reconfiguration x
3.2.4.1. Connectivity 3.2.4.2. Reconfiguration Features and Register Addressing 3.2.4.3. Dynamic Reconfiguration Guidelines
3.2.4.2. Reconfiguration Features and Register Addressing x
3.2.4.2.1. Control Registers Addresses 3.2.4.2.2. Control Registers
3.2.4.3. Dynamic Reconfiguration Guidelines x
3.2.4.3.1. Strobe Enable Window Calibration 3.2.4.3.2. Output and Strobe Enable Minimum and Maximum Phase Settings 3.2.4.3.3. Input DQ/DQS Delay Chains Maximum Values
3.3. Getting Started x
3.3.1. Parameter Settings 3.3.2. Signals
3.3.1. Parameter Settings x
3.3.1.1. Read Latency 3.3.1.2. Write Latency
3.3.2. Signals x
3.3.2.1. Clock and Reset Interface Signals 3.3.2.2. Output Path Signals 3.3.2.3. Input Path Signals
3.4. I/O Standards x
3.4.1. Input Buffer Reference Voltage (VREF) 3.4.2. On-Chip Termination (OCT)
3.4.2. On-Chip Termination (OCT) x
3.4.2.1. RZQ_GROUP Assignment
3.5. Design Guidelines x
3.5.1. Guidelines: Group Pin Placement 3.5.2. Reference Clock 3.5.3. Reset
3.6. Design Example x
3.6.1. Generate the Design Example
3.6.1. Generate the Design Example x
3.6.1.1. Design Example without Dynamic Reconfiguration 3.6.1.2. Dynamic Reconfiguration Design Examples
3.6.1.1. Design Example without Dynamic Reconfiguration x
3.6.1.1.1. Generate the Synthesis Design Example 3.6.1.1.2. Generate the Simulation Design Example
3.6.1.2. Dynamic Reconfiguration Design Examples x
3.6.1.2.1. Generate the Synthesis Design Example 3.6.1.2.2. Generate the Simulation Design Example
4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP x
4.1. Release Information 4.2. Functional Description 4.3. Getting Started 4.4. I/O Standards 4.5. Design Guidelines 4.6. Design Example
4.2. Functional Description x
4.2.1. Top Level Interfaces 4.2.2. Clocks 4.2.3. Output Path 4.2.4. Input Path 4.2.5. Dynamic Reconfiguration
4.2.2. Clocks x
4.2.2.1. Clock Frequency Relationships
4.2.3. Output Path x
4.2.3.1. Output Path Data Alignment
4.2.4. Input Path x
4.2.4.1. Input Path Data Alignment
4.2.5. Dynamic Reconfiguration x
4.2.5.1. RTL Connectivity 4.2.5.2. Address Lookup 4.2.5.3. Reconfiguration Features and Register Addressing 4.2.5.4. Calibration Guidelines
4.2.5.1. RTL Connectivity x
4.2.5.1.1. Daisy Chain
4.2.5.2. Address Lookup x
4.2.5.2.1. Strobes 4.2.5.2.2. Parameter Table Examples
4.2.5.3. Reconfiguration Features and Register Addressing x
4.2.5.3.1. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Control Registers Addresses 4.2.5.3.2. Control Registers Description
4.2.5.4. Calibration Guidelines x
4.2.5.4.1. Strobe Enable Window Calibration 4.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
4.3. Getting Started x
4.3.1. Parameter Settings 4.3.2. Signals
4.3.1. Parameter Settings x
4.3.1.1. Read Latency 4.3.1.2. Write Latency
4.3.2. Signals x
4.3.2.1. Clock and Reset Interface Signals 4.3.2.2. Output Path Signals 4.3.2.3. Input Path Signals 4.3.2.4. Avalon Configuration Bus Interface Signals 4.3.2.5. Termination Signals
4.4. I/O Standards x
4.4.1. Input Buffer Reference Voltage (VREF) 4.4.2. On-Chip Termination (OCT)
4.4.1. Input Buffer Reference Voltage (VREF) x
4.4.1.1. Calibrated VREF Settings
4.4.2. On-Chip Termination (OCT) x
4.4.2.1. RZQ_GROUP Assignment 4.4.2.2. Manual Insertion of OCT Block
4.5. Design Guidelines x
4.5.1. Guidelines: Group Pin Placement 4.5.2. Reference Clock 4.5.3. Reset 4.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 4.5.5. Dynamic Reconfiguration 4.5.6. Timing
4.5.6. Timing x
4.5.6.1. Timing Components 4.5.6.2. Timing Constraints and Files 4.5.6.3. Timing Analysis 4.5.6.4. Timing Closure Guidelines
4.5.6.2. Timing Constraints and Files x
4.5.6.2.1. <variation_name>.sdc 4.5.6.2.2. <variation_name>_parameter.tcl 4.5.6.2.3. <variation_name>_ip_parameters.tcl 4.5.6.2.4. <variation_name>_pin_map.tcl 4.5.6.2.5. <variation_name>_report_timing.tcl 4.5.6.2.6. <variation_name>_report_timing_core.tcl
4.5.6.4. Timing Closure Guidelines x
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration 4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 4.5.6.4.5. I/O Timing Violation 4.5.6.4.6. Internal FPGA Path Timing Violation
4.6. Design Example x
4.6.1. Generate the Design Example
4.6.1. Generate the Design Example x
4.6.1.1. Design Example without Dynamic Reconfiguration 4.6.1.2. Dynamic Reconfiguration Design Examples
4.6.1.1. Design Example without Dynamic Reconfiguration x
4.6.1.1.1. Generate the Hardware Design Example 4.6.1.1.2. Generate the Simulation Design Example
4.6.1.2. Dynamic Reconfiguration Design Examples x
4.6.1.2.1. Dynamic Reconfiguration Using Finite State Machine
5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs x
5.1. Release Information 5.2. Functional Description 5.3. Getting Started 5.4. I/O Standards 5.5. Design Guidelines 5.6. Design Example 5.7. Application Specific Design Example
5.2. Functional Description x
5.2.1. Top Level Interfaces 5.2.2. Clocks 5.2.3. Output Path 5.2.4. Input Path 5.2.5. Dynamic Reconfiguration
5.2.2. Clocks x
5.2.2.1. Clock Frequency Relationships
5.2.3. Output Path x
5.2.3.1. Output Path Data Alignment
5.2.4. Input Path x
5.2.4.1. Input Path Data Alignment
5.2.5. Dynamic Reconfiguration x
5.2.5.1. RTL Connectivity 5.2.5.2. Address Lookup 5.2.5.3. Reconfiguration Features and Register Addressing 5.2.5.4. Calibration Guidelines
5.2.5.1. RTL Connectivity x
5.2.5.1.1. Daisy Chain
5.2.5.2. Address Lookup x
5.2.5.2.1. Strobes 5.2.5.2.2. Parameter Table Examples
5.2.5.3. Reconfiguration Features and Register Addressing x
5.2.5.3.1. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for Parallel Interfaces Intel Cyclone 10 GX IPs Address Registers 5.2.5.3.2. Control Registers Description
5.2.5.4. Calibration Guidelines x
5.2.5.4.1. Strobe Enable Window Calibration 5.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
5.3. Getting Started x
5.3.1. Parameter Settings 5.3.2. Signals
5.3.1. Parameter Settings x
5.3.1.1. Read Latency 5.3.1.2. Write Latency
5.3.2. Signals x
5.3.2.1. Clock and Reset Interface Signals 5.3.2.2. Output Path Signals 5.3.2.3. Input Path Signals 5.3.2.4. Avalon Configuration Bus Interface Signals 5.3.2.5. Termination Signals
5.4. I/O Standards x
5.4.1. Input Buffer Reference Voltage (VREF) 5.4.2. On-Chip Termination (OCT)
5.4.1. Input Buffer Reference Voltage (VREF) x
5.4.1.1. Calibrated VREF Settings
5.4.2. On-Chip Termination (OCT) x
5.4.2.1. RZQ_GROUP Assignment 5.4.2.2. Manual Insertion of OCT Block
5.5. Design Guidelines x
5.5.1. Guidelines: Group Pin Placement 5.5.2. Reference Clock 5.5.3. Reset 5.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 5.5.5. Dynamic Reconfiguration 5.5.6. Timing
5.5.6. Timing x
5.5.6.1. Timing Components 5.5.6.2. Timing Constraints and Files 5.5.6.3. Timing Analysis 5.5.6.4. Timing Closure Guidelines
5.5.6.2. Timing Constraints and Files x
5.5.6.2.1. <variation_name>.sdc 5.5.6.2.2. <variation_name>_parameter.tcl 5.5.6.2.3. <variation_name>_ip_parameters.tcl 5.5.6.2.4. <variation_name>_pin_map.tcl 5.5.6.2.5. <variation_name>_report_timing.tcl 5.5.6.2.6. <variation_name>_report_timing_core.tcl
5.5.6.4. Timing Closure Guidelines x
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration 5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 5.5.6.4.5. I/O Timing Violation 5.5.6.4.6. Internal FPGA Path Timing Violation
5.6. Design Example x
5.6.1. Generate the Design Example
5.6.1. Generate the Design Example x
5.6.1.1. Design Example without Dynamic Reconfiguration 5.6.1.2. Dynamic Reconfiguration Design Examples
5.6.1.1. Design Example without Dynamic Reconfiguration x
5.6.1.1.1. Generate the Hardware Design Example 5.6.1.1.2. Generate the Simulation Design Example
5.6.1.2. Dynamic Reconfiguration Design Examples x
5.6.1.2.1. Dynamic Reconfiguration with Debug Kit 5.6.1.2.2. Dynamic Reconfiguration Using Finite State Machine
5.7. Application Specific Design Example x
5.7.1. Implementation using the PHY Lite for Parallel Interfaces IP
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series
3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series
4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
7. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide

2.5.2. Verify Simulation Design Examples using Tester IP

The design examples, both with dynamic reconfiguration and without dynamic reconfiguration, use Tester IP to verify PHY Lite for Parallel Interfaces IP functionality. The tester exercises read and write operations to the PHY Lite for Parallel Interfaces IP to verify its functionality.
At a high level, the tester is a state machine that repeatedly performs read/write operations. Disabling a test causes the corresponding tester state to be skipped. The following lists the tester states in the order they are performed:
  1. STATE_INIT: Initialization
  2. STATE_TEST_CALBUS: Calibration when dynamic reconfiguration is enabled
  3. STATE_TEST_WRITE: Enabled only in output and bidir modes
  4. STATE_TEST_READ: Enabled only in input and bidir modes
  5. STATE_DONE: All bursts of data successfully transmitted
The following table shows the port connections between the PHY Lite for Parallel Interfaces IP and tester. Tester ports not shown in the table are pass_out and fail_out which signal the success or failure of the test. Multiple PHY Lite for Parallel Interfaces IP groups can be tested by daisy chaining testers and connecting pass_out and fail_out of each tester to the pass_in and fail_in ports of the next tester in chain. The Calbus ports are not shown in the table as well.
Table 21.   PHY Lite for Parallel Interfaces IP for M-Series Devices and Tester Port ConnectionsThis table lists the PHY Lite and Tester port connections.
Ports Connection PHY Lite for Parallel Interfaces Ports Width Tester Ports
PHY Lite for Parallel Interfaces IP interface submodule group_X_data_from_core GROUP_DATA_WIDTH group_data_from_core
group_X_oe_from_core GROUP_CTRL_WIDTH group_oe_from_core
group_X_strobe_from_core GROUP_STROBE_WIDTH group_strobe_from_core
group_X_strobe_out_en GROUP_CTRL_WIDTH group_strobe_out_en
group_X_data_to_core GROUP_DATA_WIDTH group_data_to_core
group_X_rdata_en GROUP_CTRL_WIDTH group_rdata_en
group_X_rdata_valid GROUP_CTRL_WIDTH group_rdata_valid
I/O model group_X_data_out GROUP_PIN_WIDTH group_data_out
group_X_data_out_n GROUP_PIN_WIDTH group_data_out_n
group_X_data_in GROUP_PIN_WIDTH group_data_in
group_X_data_in_n GROUP_PIN_WIDTH group_data_in_n
group_X_data_io GROUP_PIN_WIDTH group_data_io
group_X_data_io_n GROUP_PIN_WIDTH group_data_io_n
group_X_strobe_out N/A group_strobe_out
group_X_strobe_out_n group_strobe_out_n
group_X_strobe_in group_strobe_in
group_X_strobe_in_n group_strobe_in_n
group_X_strobe_io group_strobe_io
group_X_strobe_io_n group_strobe_io_n
The tester instantiates the following three submodules:
  • I/O model: Connects to the PHY Lite for Parallel Interfaces I/O interface. Includes two instances of prbs channel, one to generate random pattern for read tests, and one to check the received pattern in the write tests.
  • PHY Lite for Parallel Interfaces IP interface: Connects to the PHY Lite for Parallel Interfaces IP core interface. Includes two instances of prbs channel, one to generate random pattern for write tests, and one to check received pattern in the read tests. Reframing logic is also included in this module.
  • IOSSM tester: Exposes an AXI4-Lite IP Interface and performs reads and writes to change the TX delay on pin 0. Only available for simulation example design with dynamic reconfiguration.
Level Two Title