PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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Date 8/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the PHY Lite for Parallel Interfaces IP 2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series 3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series 4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP 5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs 6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives 7. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
1. About the PHY Lite for Parallel Interfaces IP x
1.1. Device Family Support 1.2. Features
2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series x
2.1. Release Information 2.2. Functional Description 2.3. Getting Started 2.4. I/O Standards 2.5. Design Example
2.2. Functional Description x
2.2.1. PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP Top Level Interfaces 2.2.2. Dynamic Reconfiguration
2.2.1. PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP Top Level Interfaces x
2.2.1.1. Clocks 2.2.1.2. Output Path 2.2.1.3. Input Path
2.2.1.1. Clocks x
2.2.1.1.1. Clock Frequency Relationships
2.2.2. Dynamic Reconfiguration x
2.2.2.1. Calibration IP 2.2.2.2. Dynamic Reconfigurable Delays 2.2.2.3. Register Map
2.3. Getting Started x
2.3.1. Parameter Settings 2.3.2. Signals
2.3.2. Signals x
2.3.2.1. Clock and Reset Interface Signals 2.3.2.2. Output Path Signals 2.3.2.3. Input Path Signals
2.4. I/O Standards x
2.4.1. Design Guidelines
2.4.1. Design Guidelines x
2.4.1.1. DQS Trees 2.4.1.2. Pin Placement Restrictions
2.5. Design Example x
2.5.1. Generate the Design Example 2.5.2. Verify Simulation Design Examples using Tester IP
2.5.1. Generate the Design Example x
2.5.1.1. Design Example without Dynamic Reconfiguration 2.5.1.2. Dynamic Reconfiguration Design Examples
2.5.1.1. Design Example without Dynamic Reconfiguration x
2.5.1.1.1. Generate the Synthesis Design Example 2.5.1.1.2. Generate the Simulation Design Example
2.5.1.2. Dynamic Reconfiguration Design Examples x
2.5.1.2.1. Generate the Synthesis Design Example 2.5.1.2.2. Generate the Simulation Design Example
3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series x
3.1. Release Information 3.2. Functional Description 3.3. Getting Started 3.4. I/O Standards 3.5. Design Guidelines 3.6. Design Example
3.2. Functional Description x
3.2.1. Intel Agilex® 7 F-Series and I-Series I/O Sub-bank Interconnects 3.2.2. Intel Agilex® 7 F-Series and I-Series Input DQS/Strobe Tree 3.2.3. PHY Lite for Parallel Interfaces Intel Agilex® 7 for F-Series and I-Series FPGA IP Top Level Interfaces 3.2.4. Dynamic Reconfiguration 3.2.5. I/O Timing
3.2.3. PHY Lite for Parallel Interfaces Intel Agilex® 7 for F-Series and I-Series FPGA IP Top Level Interfaces x
3.2.3.1. Clocks 3.2.3.2. Output Path 3.2.3.3. Input Path
3.2.3.1. Clocks x
3.2.3.1.1. Clock Frequency Relationships
3.2.4. Dynamic Reconfiguration x
3.2.4.1. Connectivity 3.2.4.2. Reconfiguration Features and Register Addressing 3.2.4.3. Dynamic Reconfiguration Guidelines
3.2.4.2. Reconfiguration Features and Register Addressing x
3.2.4.2.1. Control Registers Addresses 3.2.4.2.2. Control Registers
3.2.4.3. Dynamic Reconfiguration Guidelines x
3.2.4.3.1. Strobe Enable Window Calibration 3.2.4.3.2. Output and Strobe Enable Minimum and Maximum Phase Settings 3.2.4.3.3. Input DQ/DQS Delay Chains Maximum Values
3.3. Getting Started x
3.3.1. Parameter Settings 3.3.2. Signals
3.3.1. Parameter Settings x
3.3.1.1. Read Latency 3.3.1.2. Write Latency
3.3.2. Signals x
3.3.2.1. Clock and Reset Interface Signals 3.3.2.2. Output Path Signals 3.3.2.3. Input Path Signals
3.4. I/O Standards x
3.4.1. Input Buffer Reference Voltage (VREF) 3.4.2. On-Chip Termination (OCT)
3.4.2. On-Chip Termination (OCT) x
3.4.2.1. RZQ_GROUP Assignment
3.5. Design Guidelines x
3.5.1. Guidelines: Group Pin Placement 3.5.2. Reference Clock 3.5.3. Reset
3.6. Design Example x
3.6.1. Generate the Design Example
3.6.1. Generate the Design Example x
3.6.1.1. Design Example without Dynamic Reconfiguration 3.6.1.2. Dynamic Reconfiguration Design Examples
3.6.1.1. Design Example without Dynamic Reconfiguration x
3.6.1.1.1. Generate the Synthesis Design Example 3.6.1.1.2. Generate the Simulation Design Example
3.6.1.2. Dynamic Reconfiguration Design Examples x
3.6.1.2.1. Generate the Synthesis Design Example 3.6.1.2.2. Generate the Simulation Design Example
4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP x
4.1. Release Information 4.2. Functional Description 4.3. Getting Started 4.4. I/O Standards 4.5. Design Guidelines 4.6. Design Example
4.2. Functional Description x
4.2.1. Top Level Interfaces 4.2.2. Clocks 4.2.3. Output Path 4.2.4. Input Path 4.2.5. Dynamic Reconfiguration
4.2.2. Clocks x
4.2.2.1. Clock Frequency Relationships
4.2.3. Output Path x
4.2.3.1. Output Path Data Alignment
4.2.4. Input Path x
4.2.4.1. Input Path Data Alignment
4.2.5. Dynamic Reconfiguration x
4.2.5.1. RTL Connectivity 4.2.5.2. Address Lookup 4.2.5.3. Reconfiguration Features and Register Addressing 4.2.5.4. Calibration Guidelines
4.2.5.1. RTL Connectivity x
4.2.5.1.1. Daisy Chain
4.2.5.2. Address Lookup x
4.2.5.2.1. Strobes 4.2.5.2.2. Parameter Table Examples
4.2.5.3. Reconfiguration Features and Register Addressing x
4.2.5.3.1. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Control Registers Addresses 4.2.5.3.2. Control Registers Description
4.2.5.4. Calibration Guidelines x
4.2.5.4.1. Strobe Enable Window Calibration 4.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
4.3. Getting Started x
4.3.1. Parameter Settings 4.3.2. Signals
4.3.1. Parameter Settings x
4.3.1.1. Read Latency 4.3.1.2. Write Latency
4.3.2. Signals x
4.3.2.1. Clock and Reset Interface Signals 4.3.2.2. Output Path Signals 4.3.2.3. Input Path Signals 4.3.2.4. Avalon Configuration Bus Interface Signals 4.3.2.5. Termination Signals
4.4. I/O Standards x
4.4.1. Input Buffer Reference Voltage (VREF) 4.4.2. On-Chip Termination (OCT)
4.4.1. Input Buffer Reference Voltage (VREF) x
4.4.1.1. Calibrated VREF Settings
4.4.2. On-Chip Termination (OCT) x
4.4.2.1. RZQ_GROUP Assignment 4.4.2.2. Manual Insertion of OCT Block
4.5. Design Guidelines x
4.5.1. Guidelines: Group Pin Placement 4.5.2. Reference Clock 4.5.3. Reset 4.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 4.5.5. Dynamic Reconfiguration 4.5.6. Timing
4.5.6. Timing x
4.5.6.1. Timing Components 4.5.6.2. Timing Constraints and Files 4.5.6.3. Timing Analysis 4.5.6.4. Timing Closure Guidelines
4.5.6.2. Timing Constraints and Files x
4.5.6.2.1. <variation_name>.sdc 4.5.6.2.2. <variation_name>_parameter.tcl 4.5.6.2.3. <variation_name>_ip_parameters.tcl 4.5.6.2.4. <variation_name>_pin_map.tcl 4.5.6.2.5. <variation_name>_report_timing.tcl 4.5.6.2.6. <variation_name>_report_timing_core.tcl
4.5.6.4. Timing Closure Guidelines x
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration 4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 4.5.6.4.5. I/O Timing Violation 4.5.6.4.6. Internal FPGA Path Timing Violation
4.6. Design Example x
4.6.1. Generate the Design Example
4.6.1. Generate the Design Example x
4.6.1.1. Design Example without Dynamic Reconfiguration 4.6.1.2. Dynamic Reconfiguration Design Examples
4.6.1.1. Design Example without Dynamic Reconfiguration x
4.6.1.1.1. Generate the Hardware Design Example 4.6.1.1.2. Generate the Simulation Design Example
4.6.1.2. Dynamic Reconfiguration Design Examples x
4.6.1.2.1. Dynamic Reconfiguration Using Finite State Machine
5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs x
5.1. Release Information 5.2. Functional Description 5.3. Getting Started 5.4. I/O Standards 5.5. Design Guidelines 5.6. Design Example 5.7. Application Specific Design Example
5.2. Functional Description x
5.2.1. Top Level Interfaces 5.2.2. Clocks 5.2.3. Output Path 5.2.4. Input Path 5.2.5. Dynamic Reconfiguration
5.2.2. Clocks x
5.2.2.1. Clock Frequency Relationships
5.2.3. Output Path x
5.2.3.1. Output Path Data Alignment
5.2.4. Input Path x
5.2.4.1. Input Path Data Alignment
5.2.5. Dynamic Reconfiguration x
5.2.5.1. RTL Connectivity 5.2.5.2. Address Lookup 5.2.5.3. Reconfiguration Features and Register Addressing 5.2.5.4. Calibration Guidelines
5.2.5.1. RTL Connectivity x
5.2.5.1.1. Daisy Chain
5.2.5.2. Address Lookup x
5.2.5.2.1. Strobes 5.2.5.2.2. Parameter Table Examples
5.2.5.3. Reconfiguration Features and Register Addressing x
5.2.5.3.1. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for Parallel Interfaces Intel Cyclone 10 GX IPs Address Registers 5.2.5.3.2. Control Registers Description
5.2.5.4. Calibration Guidelines x
5.2.5.4.1. Strobe Enable Window Calibration 5.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
5.3. Getting Started x
5.3.1. Parameter Settings 5.3.2. Signals
5.3.1. Parameter Settings x
5.3.1.1. Read Latency 5.3.1.2. Write Latency
5.3.2. Signals x
5.3.2.1. Clock and Reset Interface Signals 5.3.2.2. Output Path Signals 5.3.2.3. Input Path Signals 5.3.2.4. Avalon Configuration Bus Interface Signals 5.3.2.5. Termination Signals
5.4. I/O Standards x
5.4.1. Input Buffer Reference Voltage (VREF) 5.4.2. On-Chip Termination (OCT)
5.4.1. Input Buffer Reference Voltage (VREF) x
5.4.1.1. Calibrated VREF Settings
5.4.2. On-Chip Termination (OCT) x
5.4.2.1. RZQ_GROUP Assignment 5.4.2.2. Manual Insertion of OCT Block
5.5. Design Guidelines x
5.5.1. Guidelines: Group Pin Placement 5.5.2. Reference Clock 5.5.3. Reset 5.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 5.5.5. Dynamic Reconfiguration 5.5.6. Timing
5.5.6. Timing x
5.5.6.1. Timing Components 5.5.6.2. Timing Constraints and Files 5.5.6.3. Timing Analysis 5.5.6.4. Timing Closure Guidelines
5.5.6.2. Timing Constraints and Files x
5.5.6.2.1. <variation_name>.sdc 5.5.6.2.2. <variation_name>_parameter.tcl 5.5.6.2.3. <variation_name>_ip_parameters.tcl 5.5.6.2.4. <variation_name>_pin_map.tcl 5.5.6.2.5. <variation_name>_report_timing.tcl 5.5.6.2.6. <variation_name>_report_timing_core.tcl
5.5.6.4. Timing Closure Guidelines x
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration 5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 5.5.6.4.5. I/O Timing Violation 5.5.6.4.6. Internal FPGA Path Timing Violation
5.6. Design Example x
5.6.1. Generate the Design Example
5.6.1. Generate the Design Example x
5.6.1.1. Design Example without Dynamic Reconfiguration 5.6.1.2. Dynamic Reconfiguration Design Examples
5.6.1.1. Design Example without Dynamic Reconfiguration x
5.6.1.1.1. Generate the Hardware Design Example 5.6.1.1.2. Generate the Simulation Design Example
5.6.1.2. Dynamic Reconfiguration Design Examples x
5.6.1.2.1. Dynamic Reconfiguration with Debug Kit 5.6.1.2.2. Dynamic Reconfiguration Using Finite State Machine
5.7. Application Specific Design Example x
5.7.1. Implementation using the PHY Lite for Parallel Interfaces IP
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series
3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series
4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
7. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide

2.2.2.3. Register Map

The address register map addr_map.vh and a corresponding C header file are automatically created at IP generation. It contains the Avalon® memory-mapped interface registers that users can read and write to use the AXI4-Lite IP interface of the Calibration IP.

Since these registers include multiple fields for different settings, they should only be changed with read-modify-write cycle to ensure that other fields in the register remain intact. The address of a register is 24 bits, consists of an 11-bit base address right-padded with 13’b0, and a 13-bit offset address left-padded with 11’b0. The padding is done to make the base address and offset address 24 bits.

In the hardware, the addresses are automatically right-shifted to right by 2 bits. In other words, from software view the 24 bits addresses are padded by two zeros at the right. In the hardware view, the zero paddings are discarded and the address width gets reduced to 22 bits.

The base address is calculated as:

Base address = {3’b011, 3 bits instance ID, 2 bits atom ID, 3 bits lane ID},

where atom ID is 2’b00 for Byte control and 2’b01 for Byte. All the reconfigurable PHY Lite for Parallel Interfaces IP settings are in Byte control. The offset voltage for different registers in the address map, as well as bit-field description of the registers, is provided in the table below. As an example, suppose that the PHY Lite for Parallel Interfaces Instance ID is 0 and group 0 is assigned to lane 0. To change the output delay of pin 0, you need to modify the INSTANCE_0_GROUP_0_PIN_00_DDRCRTIMINGCONTROL register.

The base and offset addresses are derived as:

Base address = {3’b011, 3’b000, 2’b00, 3’b000, 13’b0} = 24’h600000

Offset address = {11’b0, 0x100} = 24’h000100

Full address = Base address + Offset address = 24’h0060_0100

An attempt to write to an invalid memory address leads to data corruption in other registers. For guidance, refer to the following table of Avalon® memory-mapped interface address registers. The Avalon® memory-mapped interface registers are 32-bit wide.

Table 13.  Address Register MapThis table shows the relevant bit-fields in the registers as they appear in the generated address map.
Register Name

Offset address

(11 bit)

 Description Bit field Bit field Description
INSTANCE_<n>_GROUP_<n>_PIN_00_DDRCRTIMINGCONTROL 0x100 DQ and DQS timing [31:21] TxDqDelay
INSTANCE_<n>_GROUP_<n>_PIN_01_DDRCRTIMINGCONTROL 0xfc
INSTANCE_<n>_GROUP_<n>_PIN_02_DDRCRTIMINGCONTROL 0xf8
INSTANCE_<n>_GROUP_<n>_PIN_03_DDRCRTIMINGCONTROL 0xf4
INSTANCE_<n>_GROUP_<n>_PIN_04_DDRCRTIMINGCONTROL 0xf0 [13:7] RxDqsNDelayPi
INSTANCE_<n>_GROUP_<n>_PIN_05_DDRCRTIMINGCONTROL 0xec
INSTANCE_<n>_GROUP_<n>_PIN_06_DDRCRTIMINGCONTROL 0xe8
INSTANCE_<n>_GROUP_<n>_PIN_07_DDRCRTIMINGCONTROL 0xe4
INSTANCE_<n>_GROUP_<n>_PIN_08_DDRCRTIMINGCONTROL 0xe0 [6:0] RxDqsPDelayPi
INSTANCE_<n>_GROUP_<n>_PIN_09_DDRCRTIMINGCONTROL 0xdc
INSTANCE_<n>_GROUP_<n>_PIN_10_DDRCRTIMINGCONTROL 0xd8
INSTANCE_<n>_GROUP_<n>_PIN_11_DDRCRTIMINGCONTROL 0xd4
INSTANCE_<n>_PHY_LANE_<n>_UPPER_NIBBLE_RCVEN 0x114 RcvEn delay for upper nibble [10:0] RxRcvEnPiRank0
INSTANCE_<n>_PHY_LANE_<n>_LOWER_NIBBLE_RCVEN 0x11c RcvEn delay for lower nibble [10:0] RxRcvEnPiRank0
INSTANCE_<n>_PHY_LANE_<n>_UPPER_NIBBLE_DATACONTROL2 0x10c DQ/DQS ODT, DQ sense amp delay and duration upper nibble [31:27] DqsSenseAmpDelay
[26:23] DqSenseAmpDuration
[22:18] DqSenseAmpDelay
[17:14] DqOdtDuration
[13:9] DqOdtDelay
[8:5] DqsOdtDuration
[4:0] DqsOdtDelay
INSTANCE_<n>_PHY_LANE_<n>_LOWER_NIBBLE_DATACONTROL2 0x110 DQ/DQS ODT, DQ sense amp delay and duration lower nibble [31:27] DqsSenseAmpDelay
[26:23] DqSenseAmpDuration
[22:18] DqSenseAmpDelay
[17:14] DqOdtDuration
[13:9] DqOdtDelay
[8:5] DqsOdtDuration
[4:0] DqsOdtDelay
INSTANCE_<n>_PHY_LANE_<n>_UPPER_NIBBLE_DQSSENSEAMPDURATION 0x124 Dqs sense amp duration upper nibble [29:26] DqsSenseAmpDuration
INSTANCE_<n>_PHY_LANE_<n>_LOWER_NIBBLE_DQSSENSEAMPDURATION 0x128 Dqs sense amp duration lower nibble [29:26] DqsSenseAmpDuration
INSTANCE_<n>_PHY_LANE_<n>_RXFIFO 0x13c Read enable offset change read valid delay [3:0] read_enable_offset
INSTANCE_<n>_PHY_LANE_<n>_DATATRAINFEEDBACK 0x160 Train reset and training mode [14] TrainReset
[9] RLTrainingMode
INSTANCE_<n>_PHY_LANE_<n>_TRAINFEEDBACK 0x1f4 Train feedback [23:12] DataTrainFeedback_N1
[11:0] DataTrainFeedback_N0
INSTANCE_<n>_PHY_LANE_<n>_DATACONTROL6 0x130 VRef I/O Voltage [29:21] RxDataVrefL
[20:12] RxDataVrefU
Level Two Title