PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 8/02/2023
Public

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2.3.1. Parameter Settings

Table 14.   PHY Lite for Parallel Interfaces IP Parameter Settings
Parameter Values Default Values Description
Parameter
Number of groups 1 - 8 1 Number of data and strobe groups in the interface. The value is set to 1 by default.
I/O Instance ID 0 - 7 0 To be used to assign different base addressed to two instances in the same bank.
General Tab- these parameters are set on a per interface basis
Clocks
Interface clock frequency

150 MHz - 1250 MHz

533.0 MHz External interface clock frequency.
Use recommended PLL reference clock frequency On, Off On

Turn this option on to calculate the PLL reference clock frequency automatically for best performance.

Turn this option off to specify your own PLL reference clock frequency.

PLL reference clock frequency Dependent on interface clock frequency 266.5 MHz

PLL reference clock frequency. You must feed a clock of this frequency to the PLL reference clock input of the memory interface.

Select the desired PLL reference clock frequency from the drop-down list. The values in the list changes when you change the interface clock frequency or the user clock rate logic.

VCO clock frequency Calculated internally by PLL 1066.0 MHz The frequency of this clock is calculated internally by the PLL based on the interface clock and the core clock rate.
Core clock frequency Calculated internally by PLL 266.5 MHz The frequency of this clock is calculated internally by the PLL based on clock rate of user logic.
Dynamic Reconfiguration
Use dynamic reconfiguration On, Off Off

Exposes an Avalon® memory-mapped interface, allowing you to control the configuration of the PHY Lite for Parallel Interfaces IP settings.

Note: The PHY Lite for Parallel Interfaces IP does not support dynamic reconfiguration feature in the Intel® Quartus® Prime version 20.3.
I/O Settings
I/O standard

SSTL-12

1.2-V POD

1.1-V POD

1.2-V HSTL

1.2-V HSUL

1.1-V LVSTL

1.05-V LVSTL

SSTL-12 Specifies the I/O standard of the interface's strobe and data pins written.
Reference clock I/O configuration

Single-ended,

True Differential with on-chip termination,

True Differential without on-chip termination

Single-ended Specifies the reference clock I/O configuration.
Group<x> - these parameters are set on a per group basis
Group<x> Pin Settings
Pin type Input, Output, Bidirectional Bidirectional Direction of data pins. This value is set to Bidirectional by default.
Pin width 1 to 22 8 Number of pins in this data/strobe group. The pin width includes the number of strobe pins.
DDR/SDR DDR, SDR DDR Double/single data rate.
Data Configuration Differential, Single-ended Differential Select the type of data.
Group<x> Input Path Settings
Additional receiver enable latency 0 to 15 0 The number of external interface clock cycles to delay the internal receiver enable signal in addition to the inherent latency in the receiver enable path. The valid range depends on the user clock rate and memory interface frequency set in the General tab.
Capture strobe phase shift 0, 45, 90 90 Internally phase shift the input strobe relative to input data.
Group<x> Output Path Settings
Additional write latency 0 to 15 0 The number of external interface clock cycles to delay the output data in addition to the inherent write latency. The valid range is the set of sub core clock cycles, which is dependent on the user clock rate set in the General tab. To delay by a larger amount, the data should be registered in the core.
Output strobe phase

0, 45, 90, 135,

180

90 Phase shift of the output strobe relative to the output data.

Group<x> General Strobe Settings

Note: These parameters are disabled when Copy parameters from another group is enabled.
Strobe configuration Differential, Single-ended Differential

Select the type of strobe.

Refer to the I/O Standards table for a list of supported I/O standards.

Group<x> OCT Settings
Use Default OCT Values On, Off On Use default OCT values based on the I/O standard parameter setting.
Input OCT Value

40 ohm with calibration,

50 ohm with calibration,

50 ohm without calibration,

60 ohm with calibration

60 ohm with calibration

Specifies the group's data and strobe input termination values.

Disables the Use Default OCT Values parameter to select the desired input OCT value.

Output OCT Value

34 ohm with calibration,

34 ohm without calibration,

40 ohm with calibration,

40 ohm without calibration

40 ohm with calibration

Specifies the group's data and strobe output termination values.

Disable the Use Default OCT Values parameter to select the desired output OCT value.

Pin Placement
RZQ Index 38, 62 38 Specifies the RZQ pin index in the I/O bank. It should be reserved at pin 38 or pin 62.

Pin Parameter Settings

Enable manual location of data pins

On, Off Off By default, all the data pins are placed in an ordered-dense format i.e., no gap pins. Enable this option if data pins are required to be spaced out i.e. with gap-pins. Adhere to all restrictions in the user guide.
Pin Placement Settings Comma separated values Provides a CSV list of pin locations one per each data pin. For example, a value of 0, 1, 8, 9 places data[0], data[1], data[2], data[3] on pin0, pin1, pin8, pin9 of IO48 Tile respectively, leaving pin2-7 not used for data. These unused pins may be used for PLL Reference Clocks, RZQ Pin or Strobes (subject to the constraints mentioned in the User Guide).