PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 8/02/2023
Public

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2.2. Functional Description

The PHY Lite for Parallel Interfaces IP utilizes the I/O banks in Intel® Agilex™ M-Series devices. Each I/O bank comprises 96 pins that are organized into eight I/O lanes of 12 pins each. Reserved pins such as strobe, refclk or RZQ cannot be used as data.
Figure 1. M-Series I/O Bank Structure (Die Top View)This figure shows the I/O bank structure of the M-Series device. The figure shows the view of the die as shown in the Intel® Quartus® Prime Chip Planner. In the Pin Planner, this corresponds to the "Bottom View". Different device packages have different number of I/O banks. Refer to the device pin-out files for available I/O banks and the locations of the SDM and HPS shared I/O banks for each device package.