PHY Lite for Parallel Interfaces FPGA IP User Guide

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ID 683716
Date 3/31/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the PHY Lite for Parallel Interfaces IP 2. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 3 C-Series Devices 3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices 4. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices 5. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices 6. PHY Lite for Parallel Interfaces FPGA IP for Stratix® 10 Devices 7. PHY Lite for Parallel Interfaces FPGA IP for Arria® 10 and Cyclone® 10 GX Devices 8. PHY Lite for Parallel Interfaces FPGA IP User Guide Document Archives 9. Document Revision History for the PHY Lite for Parallel Interfaces FPGA IP User Guide
1. About the PHY Lite for Parallel Interfaces IP x
1.1. Device Family Support 1.2. Features
2. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 3 C-Series Devices x
2.1. Release Information 2.2. Functional Description 2.3. Getting Started 2.4. I/O Standards 2.5. Design Guidelines
2.2. Functional Description x
2.2.1. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 3 C-Series Devices Top Level Interfaces 2.2.2. Dynamic Reconfiguration 2.2.3. Design Example
2.2.1. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 3 C-Series Devices Top Level Interfaces x
2.2.1.1. Clocks 2.2.1.2. Output Path 2.2.1.3. Input Path
2.2.2. Dynamic Reconfiguration x
2.2.2.1. Calibration IP 2.2.2.2. Dynamic Reconfigurable Delays 2.2.2.3. Register Map
2.2.3. Design Example x
2.2.3.1. Generate the Design Example 2.2.3.2. Verify Simulation Design Examples using Tester IP
2.2.3.1. Generate the Design Example x
2.2.3.1.1. Design Example without Dynamic Reconfiguration 2.2.3.1.2. Design Example with Dynamic Reconfiguration
2.2.3.1.1. Design Example without Dynamic Reconfiguration x
2.2.3.1.1.1. Generate the Synthesis Design Example without Dynamic Reconfiguration 2.2.3.1.1.2. Generate the Simulation Design Example Without Dynamic Reconfiguration 2.2.3.1.1.3. Run the Simulation Design Example Without Dynamic Reconfiguration
2.2.3.1.2. Design Example with Dynamic Reconfiguration x
2.2.3.1.2.1. Generate the Synthesis Design Example With Dynamic Reconfiguration 2.2.3.1.2.2. Generate the Simulation Design Example with Dynamic Reconfiguration 2.2.3.1.2.3. Run the Simulation Design Example Without Dynamic Reconfiguration
2.2.3.2. Verify Simulation Design Examples using Tester IP x
2.2.3.2.1. PHY Lite Interface 2.2.3.2.2. I/O Model 2.2.3.2.3. IOSSM Tester 2.2.3.2.4. Write Test 2.2.3.2.5. Read Test 2.2.3.2.6. Calbus Test
2.3. Getting Started x
2.3.1. Parameter Settings 2.3.2. Signals
2.3.2. Signals x
2.3.2.1. Clock and Reset Interface Signals 2.3.2.2. Output Path Signals 2.3.2.3. Input Path Signals
2.5. Design Guidelines x
2.5.1. DQS Trees 2.5.2. Pin Placement Restrictions 2.5.3. Maximum Number of DQ Data Pin Configurations
2.5.3. Maximum Number of DQ Data Pin Configurations x
2.5.3.1. Automatic and Manual Pin Placement 2.5.3.2. Single-Ended Pin Configurations 2.5.3.3. Differential Pin Configurations 2.5.3.4. Mixed Pin Configurations
3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices x
3.1. Release Information 3.2. Functional Description 3.3. Getting Started 3.4. I/O Standards 3.5. Design Example
3.2. Functional Description x
3.2.1. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices Top Level Interfaces 3.2.2. Dynamic Reconfiguration
3.2.1. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices Top Level Interfaces x
3.2.1.1. Clocks 3.2.1.2. Output Path 3.2.1.3. Input Path
3.2.2. Dynamic Reconfiguration x
3.2.2.1. Calibration IP 3.2.2.2. Dynamic Reconfigurable Delays 3.2.2.3. Register Map
3.3. Getting Started x
3.3.1. Parameter Settings 3.3.2. Signals
3.3.2. Signals x
3.3.2.1. Clock and Reset Interface Signals 3.3.2.2. Output Path Signals 3.3.2.3. Input Path Signals
3.4. I/O Standards x
3.4.1. Design Guidelines
3.4.1. Design Guidelines x
3.4.1.1. DQS Trees 3.4.1.2. Pin Placement Restrictions 3.4.1.3. Maximum Number of DQ Data Pin Configurations
3.4.1.3. Maximum Number of DQ Data Pin Configurations x
3.4.1.3.1. Automatic and Manual Pin Placement 3.4.1.3.2. Single-Ended Pin Configurations 3.4.1.3.3. Differential Pin Configurations 3.4.1.3.4. Mixed Pin Configurations
3.5. Design Example x
3.5.1. Generate the Design Example 3.5.2. Verify Simulation Design Examples using Tester IP
3.5.1. Generate the Design Example x
3.5.1.1. Design Example without Dynamic Reconfiguration 3.5.1.2. Design Example with Dynamic Reconfiguration
3.5.1.1. Design Example without Dynamic Reconfiguration x
3.5.1.1.1. Generate the Synthesis Design Example without Dynamic Reconfiguration 3.5.1.1.2. Generate the Simulation Design Example Without Dynamic Reconfiguration 3.5.1.1.3. Run the Simulation Design Example Without Dynamic Reconfiguration
3.5.1.2. Design Example with Dynamic Reconfiguration x
3.5.1.2.1. Generate the Synthesis Design Example With Dynamic Reconfiguration 3.5.1.2.2. Generate the Simulation Design Example with Dynamic Reconfiguration 3.5.1.2.3. Run the Simulation Design Example Without Dynamic Reconfiguration
3.5.2. Verify Simulation Design Examples using Tester IP x
3.5.2.1. PHY Lite Interface 3.5.2.2. I/O Model 3.5.2.3. IOSSM Tester 3.5.2.4. Write Test 3.5.2.5. Read Test 3.5.2.6. Calbus Test
4. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices x
4.1. Release Information 4.2. Functional Description 4.3. Getting Started 4.4. I/O Standards 4.5. Design Guidelines 4.6. Design Example
4.2. Functional Description x
4.2.1. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices Top Level Interfaces 4.2.2. Dynamic Reconfiguration 4.2.3. I/O Timing
4.2.1. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices Top Level Interfaces x
4.2.1.1. Clocks 4.2.1.2. Output Path 4.2.1.3. Input Path
4.2.1.1. Clocks x
4.2.1.1.1. Clock Frequency Relationships
4.2.2. Dynamic Reconfiguration x
4.2.2.1. Calibration IP 4.2.2.2. Dynamic Reconfigurable Delays 4.2.2.3. Register Map
4.3. Getting Started x
4.3.1. Parameter Settings 4.3.2. Signals
4.3.2. Signals x
4.3.2.1. Clock and Reset Interface Signals 4.3.2.2. Output Path Signals 4.3.2.3. Input Path Signals
4.5. Design Guidelines x
4.5.1. DQS Trees 4.5.2. Pin Placement Restrictions
4.6. Design Example x
4.6.1. Generating the Design Example 4.6.2. Verifying Simulation Design Examples using Tester IP
4.6.1. Generating the Design Example x
4.6.1.1. Design Example without Dynamic Reconfiguration 4.6.1.2. Dynamic Reconfiguration Design Examples
4.6.1.1. Design Example without Dynamic Reconfiguration x
4.6.1.1.1. Generating the Synthesis Design Example 4.6.1.1.2. Generating the Simulation Design Example
4.6.1.2. Dynamic Reconfiguration Design Examples x
4.6.1.2.1. Generating the Synthesis Design Example 4.6.1.2.2. Generating the Simulation Design Example
5. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices x
5.1. Release Information 5.2. Functional Description 5.3. Getting Started 5.4. I/O Standards 5.5. Design Guidelines 5.6. Design Example
5.2. Functional Description x
5.2.1. Agilex™ 7 F-Series and I-Series I/O Sub-bank Interconnects 5.2.2. Agilex™ 7 F-Series and I-Series Input DQS/Strobe Tree 5.2.3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices Top Level Interfaces 5.2.4. Dynamic Reconfiguration 5.2.5. I/O Timing
5.2.3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices Top Level Interfaces x
5.2.3.1. Clocks 5.2.3.2. Output Path 5.2.3.3. Input Path
5.2.3.1. Clocks x
5.2.3.1.1. Clock Frequency Relationships
5.2.4. Dynamic Reconfiguration x
5.2.4.1. Connectivity 5.2.4.2. Reconfiguration Features and Register Addressing 5.2.4.3. Dynamic Reconfiguration Guidelines
5.2.4.2. Reconfiguration Features and Register Addressing x
5.2.4.2.1. Control Registers Addresses 5.2.4.2.2. Control Registers
5.2.4.3. Dynamic Reconfiguration Guidelines x
5.2.4.3.1. Strobe Enable Window Calibration 5.2.4.3.2. Output and Strobe Enable Minimum and Maximum Phase Settings 5.2.4.3.3. Input DQ/DQS Delay Chains Maximum Values
5.3. Getting Started x
5.3.1. Parameter Settings 5.3.2. Signals
5.3.1. Parameter Settings x
5.3.1.1. Read Latency 5.3.1.2. Write Latency
5.3.2. Signals x
5.3.2.1. Clock and Reset Interface Signals 5.3.2.2. Output Path Signals 5.3.2.3. Input Path Signals
5.4. I/O Standards x
5.4.1. Input Buffer Reference Voltage (VREF) 5.4.2. On-Chip Termination (OCT)
5.4.2. On-Chip Termination (OCT) x
5.4.2.1. RZQ_GROUP Assignment
5.5. Design Guidelines x
5.5.1. Guidelines: Group Pin Placement 5.5.2. Reference Clock 5.5.3. Reset
5.6. Design Example x
5.6.1. Generating the Design Example
5.6.1. Generating the Design Example x
5.6.1.1. Design Example without Dynamic Reconfiguration 5.6.1.2. Dynamic Reconfiguration Design Examples
5.6.1.1. Design Example without Dynamic Reconfiguration x
5.6.1.1.1. Generating the Synthesis Design Example 5.6.1.1.2. Generating the Simulation Design Example
5.6.1.2. Dynamic Reconfiguration Design Examples x
5.6.1.2.1. Generating the Synthesis Design Example 5.6.1.2.2. Generating the Simulation Design Example
6. PHY Lite for Parallel Interfaces FPGA IP for Stratix® 10 Devices x
6.1. Release Information 6.2. Functional Description 6.3. Getting Started 6.4. I/O Standards 6.5. Design Guidelines 6.6. Design Example
6.2. Functional Description x
6.2.1. Top Level Interfaces 6.2.2. Clocks 6.2.3. Output Path 6.2.4. Input Path 6.2.5. Dynamic Reconfiguration
6.2.2. Clocks x
6.2.2.1. Clock Frequency Relationships
6.2.3. Output Path x
6.2.3.1. Output Path Data Alignment
6.2.4. Input Path x
6.2.4.1. Input Path Data Alignment
6.2.5. Dynamic Reconfiguration x
6.2.5.1. RTL Connectivity 6.2.5.2. Address Lookup 6.2.5.3. Reconfiguration Features and Register Addressing 6.2.5.4. Calibration Guidelines
6.2.5.1. RTL Connectivity x
6.2.5.1.1. Daisy Chain
6.2.5.2. Address Lookup x
6.2.5.2.1. Strobes 6.2.5.2.2. Parameter Table Examples
6.2.5.3. Reconfiguration Features and Register Addressing x
6.2.5.3.1. PHY Lite for Parallel Interfaces FPGA IP for Stratix® 10 Devices Control Registers Addresses 6.2.5.3.2. Control Registers Description
6.2.5.4. Calibration Guidelines x
6.2.5.4.1. Strobe Enable Window Calibration 6.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
6.3. Getting Started x
6.3.1. Parameter Settings 6.3.2. Signals
6.3.1. Parameter Settings x
6.3.1.1. Read Latency 6.3.1.2. Write Latency
6.3.2. Signals x
6.3.2.1. Clock and Reset Interface Signals 6.3.2.2. Output Path Signals 6.3.2.3. Input Path Signals 6.3.2.4. Avalon Configuration Bus Interface Signals 6.3.2.5. Termination Signals
6.4. I/O Standards x
6.4.1. Input Buffer Reference Voltage (VREF) 6.4.2. On-Chip Termination (OCT)
6.4.1. Input Buffer Reference Voltage (VREF) x
6.4.1.1. Calibrated VREF Settings
6.4.2. On-Chip Termination (OCT) x
6.4.2.1. RZQ_GROUP Assignment 6.4.2.2. Manual Insertion of OCT Block
6.5. Design Guidelines x
6.5.1. Guidelines: Group Pin Placement 6.5.2. Reference Clock 6.5.3. Reset 6.5.4. Constraining Multiple PHY Lite for Parallel Interfaces FPGA IP to One I/O Bank 6.5.5. Dynamic Reconfiguration 6.5.6. Timing
6.5.6. Timing x
6.5.6.1. Timing Components 6.5.6.2. Timing Constraints and Files 6.5.6.3. Timing Analysis 6.5.6.4. Timing Closure Guidelines
6.5.6.2. Timing Constraints and Files x
6.5.6.2.1. <variation_name>.sdc 6.5.6.2.2. <variation_name>_parameter.tcl 6.5.6.2.3. <variation_name>_ip_parameters.tcl 6.5.6.2.4. <variation_name>_pin_map.tcl 6.5.6.2.5. <variation_name>_report_timing.tcl 6.5.6.2.6. <variation_name>_report_timing_core.tcl
6.5.6.4. Timing Closure Guidelines x
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration 6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 6.5.6.4.5. I/O Timing Violation 6.5.6.4.6. Internal FPGA Path Timing Violation
6.6. Design Example x
6.6.1. Generating the Design Example
6.6.1. Generating the Design Example x
6.6.1.1. Design Example without Dynamic Reconfiguration 6.6.1.2. Dynamic Reconfiguration Design Examples
6.6.1.1. Design Example without Dynamic Reconfiguration x
6.6.1.1.1. Generating the Hardware Design Example 6.6.1.1.2. Generating the Simulation Design Example
6.6.1.2. Dynamic Reconfiguration Design Examples x
6.6.1.2.1. Dynamic Reconfiguration Using Finite State Machine
7. PHY Lite for Parallel Interfaces FPGA IP for Arria® 10 and Cyclone® 10 GX Devices x
7.1. Release Information 7.2. Functional Description 7.3. Getting Started 7.4. I/O Standards 7.5. Design Guidelines 7.6. Design Example 7.7. Application Specific Design Example
7.2. Functional Description x
7.2.1. Top Level Interfaces 7.2.2. Clocks 7.2.3. Output Path 7.2.4. Input Path 7.2.5. Dynamic Reconfiguration
7.2.2. Clocks x
7.2.2.1. Clock Frequency Relationships
7.2.3. Output Path x
7.2.3.1. Output Path Data Alignment
7.2.4. Input Path x
7.2.4.1. Input Path Data Alignment
7.2.5. Dynamic Reconfiguration x
7.2.5.1. RTL Connectivity 7.2.5.2. Address Lookup 7.2.5.3. Reconfiguration Features and Register Addressing 7.2.5.4. Calibration Guidelines
7.2.5.1. RTL Connectivity x
7.2.5.1.1. Daisy Chain
7.2.5.2. Address Lookup x
7.2.5.2.1. Strobes 7.2.5.2.2. Parameter Table Examples
7.2.5.3. Reconfiguration Features and Register Addressing x
7.2.5.3.1. PHY Lite for Parallel Interfaces FPGA IP for Arria® 10 and Cyclone® 10 GX Address Registers 7.2.5.3.2. Control Registers Description
7.2.5.4. Calibration Guidelines x
7.2.5.4.1. Strobe Enable Window Calibration 7.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
7.3. Getting Started x
7.3.1. Parameter Settings 7.3.2. Signals
7.3.1. Parameter Settings x
7.3.1.1. Read Latency 7.3.1.2. Write Latency
7.3.2. Signals x
7.3.2.1. Clock and Reset Interface Signals 7.3.2.2. Output Path Signals 7.3.2.3. Input Path Signals 7.3.2.4. Avalon Configuration Bus Interface Signals 7.3.2.5. Termination Signals
7.4. I/O Standards x
7.4.1. Input Buffer Reference Voltage (VREF) 7.4.2. On-Chip Termination (OCT)
7.4.1. Input Buffer Reference Voltage (VREF) x
7.4.1.1. Calibrated VREF Settings
7.4.2. On-Chip Termination (OCT) x
7.4.2.1. RZQ_GROUP Assignment 7.4.2.2. Manual Insertion of OCT Block
7.5. Design Guidelines x
7.5.1. Guidelines: Group Pin Placement 7.5.2. Reference Clock 7.5.3. Reset 7.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 7.5.5. Dynamic Reconfiguration 7.5.6. Timing
7.5.6. Timing x
7.5.6.1. Timing Components 7.5.6.2. Timing Constraints and Files 7.5.6.3. Timing Analysis 7.5.6.4. Timing Closure Guidelines
7.5.6.2. Timing Constraints and Files x
7.5.6.2.1. <variation_name>.sdc 7.5.6.2.2. <variation_name>_parameter.tcl 7.5.6.2.3. <variation_name>_ip_parameters.tcl 7.5.6.2.4. <variation_name>_pin_map.tcl 7.5.6.2.5. <variation_name>_report_timing.tcl 7.5.6.2.6. <variation_name>_report_timing_core.tcl
7.5.6.4. Timing Closure Guidelines x
7.5.6.4.1. Timing Closure: Dynamic Reconfiguration 7.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 7.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 7.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 7.5.6.4.5. I/O Timing Violation 7.5.6.4.6. Internal FPGA Path Timing Violation
7.6. Design Example x
7.6.1. Generating the Design Example
7.6.1. Generating the Design Example x
7.6.1.1. Design Example without Dynamic Reconfiguration 7.6.1.2. Dynamic Reconfiguration Design Examples
7.6.1.1. Design Example without Dynamic Reconfiguration x
7.6.1.1.1. Generating the Hardware Design Example 7.6.1.1.2. Generating the Simulation Design Example
7.6.1.2. Dynamic Reconfiguration Design Examples x
7.6.1.2.1. Dynamic Reconfiguration with Debug Kit 7.6.1.2.2. Dynamic Reconfiguration Using Finite State Machine
7.7. Application Specific Design Example x
7.7.1. Implementation using the PHY Lite for Parallel Interfaces FPGA IP
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 3 C-Series Devices
3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices
4. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices
5. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices
6. PHY Lite for Parallel Interfaces FPGA IP for Stratix® 10 Devices
7. PHY Lite for Parallel Interfaces FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
8. PHY Lite for Parallel Interfaces FPGA IP User Guide Document Archives
9. Document Revision History for the PHY Lite for Parallel Interfaces FPGA IP User Guide

4.2.1.3. Input Path

The simplified input path of the IP consists of the pipeline registers, receiver FIFO, shift registers, and phase shift logics.
Figure 77. Simplified Input PathThis figure shows the input path for the PHY Lite for Parallel Interfaces FPGA IP.
Table 75.  Components in the Simplified Input Path of the PHY Lite for Parallel Interfaces FPGA IP
Component Description
Pipeline Registers Represent pipeline stages in the input path
Two RX FIFOs

Perform 2:1 rate conversion on the RX data

  • At positive edge of strobe_in signal
  • At negative edge of strobe_in signal
Shift Registers Perform the following functions:
  • Delay the RcvEn signal in VCO cycle increments
  • The read_enable_offset shift register delays the rdata_valid signal
Phase Shift Logics Perform the following functions:
  • Delay RcvEn signal in 1/128 VCO cycle increments
  • Delay RxDqsNDelayPi/RxDqsPDelayPi signal

There are five types of delay in the input path. The following table describes the delays:

Table 76.  Types of Delay in the Input Path
Delay Type Description
Inherent latency Static Captured in pipeline stages from the assertion of rdata_en signal in core until internal signal, RcvEn, is asserted.
RcvEn delay (internal signal generated from input signal rdata_en) Dynamic You can reconfigure these delays in the control registers. You can program the RcvEn delay statically or dynamically through the Additional Receiver Enable Latency settings in the IP Parameter Editor.
Positive-edge strobe_in delay Dynamic
Negative-edge strobe_in delay Dynamic
read_enable_offset delay Dynamic
Table 77.  Input Path Reconfigurable Delays DescriptionThis table lists the reconfigurable input path delays for the PHY Lite for Parallel Interfaces FPGA IP.
Feature Description Bit-field Description Min Max

RxRcvEnPiRank0

[10:7]
  • RcvEn delay
  • There are two RxRcvEnPiRank0 registers per lane. One controls the lower nibble (6 pins) and the other controls the upper nibble of the lane.
  • In PHY Lite IP, the nibbles cannot be used independently. Both control signals must be programmed to the same value.
 Bit 10 to bit 7 represents integer number of VCO clock cycles to delay RcvEn signal. 0 15

RxRcvEnPiRank0

[6:0]

 Bit 6 to bit 0 represents additional phase shift in RcvEn signal measured in 1/128 of VCO clock period. 0 127

RxDqsNDelayPi

[6:0]
  • strobe­_in delay
  • There are two RxDqsNDelayPi and RxDqsPDelayPi for each pin. Each pin receives a copy of the DQS and can phase-shift each edge of the DQS independently of other pins.
  • Usually both edges should be set to the same delay value, but different values can be used to correct uneven duty cycle.
  • The effective range of this delay setting is up to 1 VCO clock cycle.
 Phase shift in the negative edge of the DQS for each pin measured in 1/128 of VCO clock period. 0 127

RxDqsPDelayPi

[6:0]

 Phase shift in the positive edge of the DQS for each pin measured in 1/128 of VCO clock period. 0 127

read_enable_offset

[3:0]
  • rdata_valid delay
  • An adjustable setting that changes the delay before starting to read from the RX FIFO, effectively delaying the rdata_valid signal.
  • This delay setting is downstream from the integer portion of the RcvEn delay, so any additional RcvEn delay applies to the rdata_valid signal as well.
Delay before reading from the RX FIFO measured in number of PHY clock cycles. 0 15
Figure 78.  PHY Lite for Parallel Interfaces FPGA IP Input Operation

The preceding figure shows an example of RX data transfer in QR DDR. The data_to_core signal for each pin is eight bits wide. The PHY Lite for Parallel Interfaces IP uses DDR4 preamble settings, and expects one cycle of preamble by default. To set the PHY Lite for Parallel Interfaces IP to accept edge-aligned data, select 90 degrees in the Capture strobe phase shift parameter setting.

To ensure that the IP uses only clock edges associated with valid input data, gate the receiver off when PHY Lite for Parallel Interfaces IP is not accepting input data. If there are extra toggling signals or noise on the DQS port, use a refined version of the received strobe. The gating signal, RcvEn (receiver enable), is derived internally from the rdata_en signal. Use the RcvEn signal to ungate the DQS gate window by asserting RcvEn up to one cycle before the first rising edge of DQS, as shown in the following figure. You require no more than one cycle preamble in the strobe signal.

Figure 79. Ungating DQS Gate WindowThis figure shows the ungating of the DQS window by internally asserting the RcvEn signal.
Figure 80. Shutting Off the DQS Gate WindowThe following figure shows how disabling RcvEn shuts off the DQS gate.

In the input path, program the on die termination (ODT) and sense amplifier (SA) when you dynamically reconfigure the RcvEn delay.

Whenever you reconfigure the RcvEn delay, reconfigure the following ODT and SA settings to ensure that all parts of the receiver circuitry turns on at the correct time:
  • DqsSenseAmpDelay
  • DqsSenseAmpDuration
  • DqSenseAmpDuration
  • DqSenseAmpDelay
  • DqOdtDuration
  • DqOdtDelay
  • DqsOdtDuration
  • DqsOdtDelay
Adjust these settings for both upper and lower nibbles in the lane according to the following table for quarter-rate mode.
Table 78.  Settings for DQ/DQS ODT/SA DelaysThis table lists the settings adjustments for both the upper and lower nibbles in the lane for quarter-rate mode.
RxRcvEnPi[10:8] DqsOdtDelay DqOdtDelay Dq/Dqs SenseAmpDelay
0 2 3 3
1 3 4 4
2 4 5 5
3 5 6 6
4 6 7 7
5 7 8 8
6 8 9 9
7 9 10 10

For half-rate and full-rate modes, the DQ/DQS ODT/SA delay settings are set internally to zero and do not need to be adjusted.

When changing the RcvEn coarse delay or RxRcvEnPiRank0[10:7], Altera recommends that you update read_enable_offset to avoid receiving misaligned data in the core. The small values of read_enable_offset can cause RX FIFO underflow, while large values may cause an overflow.

Table 79.  Allowed values for read_enable_offset based on RcvEn coarse delayThis table lists the allowed values for read_enable_offset according to the RcvEn coarse delay.
RxRcvEnPiRank0[10:7] Allowed values for read_enable_offset
0, 1, 4, 5, 8, 9, 12, 13 3, 5, 7, 9, 11
2, 3, 6, 7, 10, 11, 14, 15 4, 6, 8, 10, 12
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