PHY Lite for Parallel Interfaces FPGA IP User Guide

ID 683716
Date 3/31/2025
Public
Document Table of Contents

4.2.1. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices Top Level Interfaces

For M-Series devices, the PHY Lite for Parallel Interfaces FPGA IP consists of the following modules:

  • Clocks and reset
  • Fabric
  • PHY data and control
  • I/O
Figure 74. Diagram of the PHY Lite for Parallel Interfaces FPGA IP for M-Series Devices