PHY Lite for Parallel Interfaces FPGA IP User Guide

ID 683716
Date 3/31/2025
Public
Document Table of Contents

3.4.1.3.1. Automatic and Manual Pin Placement

The IP Parameter Editor of the PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series devices allows automatic pin placement, as shown in the following figure. To manually place the pins, check the Enable manual location of data pins checkbox as shown in the next figure.

Figure 53. Automatic placement of data pins in PHY Lite IP Parameter Editor
Figure 54. Enable Manual Location of Data Pins in PHY Lite IP Parameter Editor

Although the ref_clk is not visible in the IP Parameter Editor, Altera recommends 1 or 2 pins to be reserved for single-ended or differential ref_clk in the IO96 bank where the PHY Lite IP is to be placed. The following error message will be displayed in the System Messages panel of the IP Parameter Editor if no pin is reserved for the ref_clk and using automatic pin placement.

THIS PHYLITE IP REQUIRES A TOTAL OF N DATA PINS. ONLY N-1 DATA PINS SUPPORTED FOR SELECTED CONFIGURATION.
Figure 55. Error Message in PHY Lite IP Parameter Editor if No Pin is Reserved for ref_clk

If the ref_clk is not reserved in any of the eight dedicated pins, the following error message will be displayed in the System Messages panel of the IP Parameter Editor.

REFCLK MUST BE PLACED EITHER ON PIN 34, 35, 36, 37, 58, 59, 60 OR 61. ALL THESE PINS ARE CURRENTLY ASSIGNED AS DATA PINS.
Figure 56. Error Message in PHY Lite IP Parameter Editor if ref_clk is Not Reserved in Any of the Eight Dedicated Pins
The reset_n port of the PHY Lite IP can be driven internally, for example, by using a reset handler module, instead of utilizing a physical pin