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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 3 C-Series Devices
3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices
4. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices
5. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices
6. PHY Lite for Parallel Interfaces FPGA IP for Stratix® 10 Devices
7. PHY Lite for Parallel Interfaces FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
8. PHY Lite for Parallel Interfaces FPGA IP User Guide Document Archives
9. Document Revision History for the PHY Lite for Parallel Interfaces FPGA IP User Guide
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration
6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
6.5.6.4.5. I/O Timing Violation
6.5.6.4.6. Internal FPGA Path Timing Violation
7.5.6.4.1. Timing Closure: Dynamic Reconfiguration
7.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
7.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
7.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
7.5.6.4.5. I/O Timing Violation
7.5.6.4.6. Internal FPGA Path Timing Violation
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5.2.5. I/O Timing
You are advised to design the system with the worst case losses for the PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series devices.
Data Flow Direction | Applies to PHY Lite for Parallel Interfaces FPGA IP Mode | Worst Case Losses6 |
---|---|---|
Driving (PHY Lite for Parallel Interfaces FPGA IP is driving the I/Os) | Output / bi-directional | 45% UI |
Receiving (PHY Lite for Parallel Interfaces FPGA IP is sampling the I/Os) | Input / bi-directional | POD 1.2 V: 38% UI SSTL 1.2 V: 49% UI |
6 The losses are denoted for a PHY Lite for Parallel Interfaces FPGA IP operating at 1,200 MHZ at DDR.