PHY Lite for Parallel Interfaces FPGA IP User Guide

ID 683716
Date 3/31/2025
Public
Document Table of Contents

5.2.5. I/O Timing

You are advised to design the system with the worst case losses for the PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series devices.

Table 104.  Worst Case Losses for PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series DevicesThis table assumes that a PHY Lite for Parallel Interfaces FPGA IP is communicating with another PHY Lite for Parallel Interfaces FPGA IP.
Data Flow Direction Applies to PHY Lite for Parallel Interfaces FPGA IP Mode Worst Case Losses6
Driving (PHY Lite for Parallel Interfaces FPGA IP is driving the I/Os) Output / bi-directional 45% UI
Receiving (PHY Lite for Parallel Interfaces FPGA IP is sampling the I/Os) Input / bi-directional

POD 1.2 V: 38% UI

SSTL 1.2 V: 49% UI

6 The losses are denoted for a PHY Lite for Parallel Interfaces FPGA IP operating at 1,200 MHZ at DDR.