PHY Lite for Parallel Interfaces FPGA IP User Guide

ID 683716
Date 3/31/2025
Public
Document Table of Contents

7.7. Application Specific Design Example

This design example demonstrates the PHY Lite for Parallel Interfaces FPGA IP implementation for a NAND Flash design in Arria® 10 devices.

The following figure shows the RTL view of the design example.

Figure 213.  RTL Viewer for a NAND Flash Simple Design Based on the PHY Lite for Parallel Interfaces FPGA IP