Visible to Intel only — GUID: asd1601257352832
Ixiasoft
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 3 C-Series Devices
3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices
4. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices
5. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices
6. PHY Lite for Parallel Interfaces FPGA IP for Stratix® 10 Devices
7. PHY Lite for Parallel Interfaces FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
8. PHY Lite for Parallel Interfaces FPGA IP User Guide Document Archives
9. Document Revision History for the PHY Lite for Parallel Interfaces FPGA IP User Guide
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration
6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
6.5.6.4.5. I/O Timing Violation
6.5.6.4.6. Internal FPGA Path Timing Violation
7.5.6.4.1. Timing Closure: Dynamic Reconfiguration
7.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
7.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
7.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
7.5.6.4.5. I/O Timing Violation
7.5.6.4.6. Internal FPGA Path Timing Violation
Visible to Intel only — GUID: asd1601257352832
Ixiasoft
5.2.1. Agilex™ 7 F-Series and I-Series I/O Sub-bank Interconnects
There are interconnects between the sub-banks which chain the sub-banks into a row. The following figures show how I/O lanes in various sub-banks are chained together to form the top and bottom I/O rows in various Agilex™ 7 device variants. These figures represent the top view of the silicon die that corresponds to a reverse view of the device package. Each sub-bank is labeled with an ID number to facilitate pin placement.
Figure 89. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGF006 and AGF008, Package R16A
Figure 90. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGF006 and AGF008, Package R16A
Figure 91. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGF012 and AGF014, Package R24B
Figure 92. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGF012 and AGF014, Package R24B
Figure 93. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGF006 and AGF008, Package R24C
Figure 94. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGF006 and AGF008, Package R24C
Figure 95. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGF014, Package R24C
Figure 96. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGF014, Package R24C
Figure 97. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGF012 and AGF014, Package R24C
Figure 98. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGF012 and AGF014, Package R24C
Figure 99. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGF019 and AGF023, Package R24C
Figure 100. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGF019 and AGF023, Package R24C
Figure 101. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGF022 and AGF027, Package R24C
Figure 102. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGF022 and AGF027, Package R24C
Figure 103. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGF019 and AGF023, Package R25A
Figure 104. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGF019 and AGF023, Package R25A
Figure 105. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGF022 and AGF027 Devices, Package R25A
Figure 106. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGF022 and AGF027 Devices, Package R25A
Figure 107. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGF019 and AGF023 Devices, Package R31C
Figure 108. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGF019 and AGF023 Devices, Package R31C
Figure 109. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGF022 and AGF027 Devices, Package R31C
Figure 110. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGF022 and AGF027 Devices, Package R31C
Figure 111. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGI019 and AGI023, Package R18A
Figure 112. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGI019 and AGI023, Package R18A
Figure 113. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGI022 and AGI027 Devices, Package R29A
Figure 114. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGI022 and AGI027 Devices, Package R29A
Figure 115. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGI027 Devices, Package R29B
Figure 116. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGI027 Devices, Package R29B
Figure 117. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGI041 Devices, Package R29D
Figure 118. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGI041 Devices, Package R29D
Figure 119. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGI022 and AGI027 Devices, Package R31A
Figure 120. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGI022 and AGI027 Devices, Package R31A
Figure 121. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGI019 and AGI023 Devices, Package R31B
Figure 122. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGI019 and AGI023 Devices, Package R31B
Figure 123. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGI022 and AGI027 Devices, Package R31B
Figure 124. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGI022 and AGI027 Devices, Package R31B
Figure 125. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGI041 Devices, Package R31B
Figure 126. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGI041 Devices, Package R31B
Figure 127. Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGI035 and AGI040 Devices, Package R39A
Figure 128. Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGI035 and AGI040 Devices, Package R39A
Related Information