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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 3 C-Series Devices
3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices
4. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices
5. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices
6. PHY Lite for Parallel Interfaces FPGA IP for Stratix® 10 Devices
7. PHY Lite for Parallel Interfaces FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
8. PHY Lite for Parallel Interfaces FPGA IP User Guide Document Archives
9. Document Revision History for the PHY Lite for Parallel Interfaces FPGA IP User Guide
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration
6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
6.5.6.4.5. I/O Timing Violation
6.5.6.4.6. Internal FPGA Path Timing Violation
7.5.6.4.1. Timing Closure: Dynamic Reconfiguration
7.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
7.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
7.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
7.5.6.4.5. I/O Timing Violation
7.5.6.4.6. Internal FPGA Path Timing Violation
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7.6. Design Example
The PHY Lite for Parallel Interfaces FPGA IP is able to generate a design example that matches the same configuration chosen for the IP. The design example is a simple design that does not target any specific application; however you can use the design example as a reference on how to instantiate the IP and what behavior to expect in a simulation.
Note: The .qsys files are for internal use during design example generation only. You should not edit the files.