PHY Lite for Parallel Interfaces FPGA IP User Guide

ID 683716
Date 3/31/2025
Public
Document Table of Contents

7.6.1.1. Design Example without Dynamic Reconfiguration

When the Enable dynamic reconfiguration option is not selected, Quartus® Prime software generates a design example of PHY Lite for Parallel Interfaces FPGA IP without a dynamic reconfiguration module.

This design example consists of simulation and synthesis design files.