External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021
Public
Document Table of Contents

4.1.1.10. afi_reset_n for DDR3

AFI reset interface

Table 18.  Interface: afi_reset_nInterface type: Reset Output
Port Name Direction Description
afi_reset_n Output Reset for the AFI clock domain. Asynchronous assertion and synchronous deassertion