Visible to Intel only — GUID: mwh1410384101674
Ixiasoft
Visible to Intel only — GUID: mwh1410384101674
Ixiasoft
1.3.2.1. Using Simulation Signal Activity Data in Power Analysis
You can specify a Verilog Value Change Dump File (.vcd) generated by a supported1 simulator as the source of signal activity data for power analysis.
Third-party simulators can output a .vcd that contains signal activity and static probability information that inform the power analysis. The generated .vcd includes all of the routing resources and the exact logic array resource usage.
For third-party simulators, use the EDA Tool Settings to specify the Generate Value Change Dump (VCD) file script option in the Simulation page of the Settings dialog box. These scripts instruct the third-party simulators to generate a .vcd that encodes the simulated waveforms. The Intel® Quartus® Prime Power Analyzer reads this file directly to derive the toggle rate and static probability data for each signal.