Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization

ID 683506
Date 12/07/2020
Public
Document Table of Contents

2.5.5. Memory Optimization (M20K/MLAB)

M20K memory blocks represent a big part of the power consumption in a design. The Fitter RAM Summary Report displays the utilization of the memory blocks in different parts of the design.
Figure 33. Fitter RAM Summary Report

Some guidelines to optimize the use of memories are:

  • Port shallow memories from M20K to MLAB.
    For example, implement in HDL with ramstyle attribute:
    (* ramstyle = "MLAB" *) reg [0:7] my_ram[0:63];
  • Avoid read-during-write behavior and set to Don’t care (at the HDL level) wherever possible.
    Read-during-write behavior impact the power of single-port and bidirectional dual-port RAMs. Don’t care allows an optimization that sets the read-enable signal to the inversion of the existing write-enable signal (if one exists). This allows the core of the RAM to shut down, which prevents switching, saving a significant amount of power.
  • Pack input/output registers in M20K.

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